160 * In Tricore Cpu the cache enable/ disable are handled by the feature called cache bypass.
161 * Cache is enabled if the Bypass is disabled.
162 *
163 * Startup sequence of each CPU execute the function to do the cache settings. \ref Ifx_Cpu_StartupSequence
164 * The configuration parameters IFX_CFG_CPU_CSTART_ENABLE_TRICOREx_PCACHE and
165 * IFX_CFG_CPU_CSTART_ENABLE_TRICOREx_DCACHE control this function.
166 *
167 * To modify the default configuration, these macros are to be defined in Ifx_Cfg.h (usually located under ../0_Src/0_AppSw/Config/Common/Ifx_Cfg.h)
168 * \note This kind of definitions overload the macros, which are already defined in IfxCpu_CStart*.c.
169 * !!IMPORTANT!! Don't modify these in IfxCpu_CStart*.c, because theseare library files.
170 *
171 * Details of configuration parameters:\n
172 *
173 * \paragraph IfxLld_Cpu_CStart_ConfigEnableCachePgmParamters program cache configuration parameters
174 *
175 * Enable/Disable program cache of Tricore CPU0 with parameter:\n
176 * IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_PCACHE\n
177 *
178 * Enable/Disable program cache of Tricore CPU1 with parameter:\n
179 * IFX_CFG_CPU_CSTART_ENABLE_TRICORE1_PCACHE\n
180 *
181 * Enable/Disable program cache of Tricore CPU2 with parameter:\n
182 * IFX_CFG_CPU_CSTART_ENABLE_TRICORE2_PCACHE\n
183 *
184 * Enable/Disable data cache of Tricore CPU0 with parameter:\n
185 * IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_DCACHE\n
186 *
187 * Enable/Disable data cache of Tricore CPU1 with parameter:\n
188 * IFX_CFG_CPU_CSTART_ENABLE_TRICORE1_DCACHE\n
189 *
190 * Enable/Disable data cache of Tricore CPU2 with parameter:\n
191 * IFX_CFG_CPU_CSTART_ENABLE_TRICORE2_DCACHE\n
192 *
193 * Following example shows, how to enable program cache of all available cores and disable data cache of all
194 * the available cores.
195 * \code
196 * //file: Ifx_Cfg.h
197 *
198 * #define IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_PCACHE (1) //Program cache for Cpu0 is enabled
199 *
200 * #define IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_DCACHE (1) //Data cache for Cpu0 is enabled
201 *
202 * #define IFX_CFG_CPU_CSTART_ENABLE_TRICORE1_PCACHE (1) //Program cache for Cpu1 is enabled
203 *
204 * #define IFX_CFG_CPU_CSTART_ENABLE_TRICORE1_DCACHE (1) //Data cache for Cpu1 is enabled
205 *
206 * #define IFX_CFG_CPU_CSTART_ENABLE_TRICORE2_PCACHE (1) //Program cache for Cpu2 is enabled
207 *
208 * #define IFX_CFG_CPU_CSTART_ENABLE_TRICORE2_DCACHE (1) //Data cache for Cpu2 is enabled
209 *
210 * \endcode
211 *
212 * To control the the caches during runtime, refer for the details of APIs: \ref Ifx_Cpu_Cache