|
| enum | IfxMsc_ActivePhaseSelection {
IfxMsc_ActivePhaseSelection_none = 0,
IfxMsc_ActivePhaseSelection_lowLevel = 1
} |
| | Enable SRL/SRH Active Phase Selection Bit
Definition in Ifx_MSC.DSC.B.ENSELH and Ifx_MSC.DSC.B.ENSELL. More...
|
| |
| enum | IfxMsc_AsynchronousBlock {
IfxMsc_AsynchronousBlock_bypassed = 0,
IfxMsc_AsynchronousBlock_noBypassed = 1
} |
| | Asynchronous Block Configuration Register - Asynchronous Block Bypass
Definition in Ifx_MSC.ABC.B.ABB. More...
|
| |
| enum | IfxMsc_ChipSelectActiveState {
IfxMsc_ChipSelectActiveState_high = 0,
IfxMsc_ChipSelectActiveState_low = 1
} |
| | Output Control Register - Chip Selection Line Polarity
Definition in Ifx_MSC.OCR.B.CSLP. More...
|
| |
| enum | IfxMsc_ClockSelect {
IfxMsc_ClockSelect_noClock = 0,
IfxMsc_ClockSelect_fspb = 1,
IfxMsc_ClockSelect_fsri = 2,
IfxMsc_ClockSelect_feray = 4
} |
| | Asynchronous Block Configuration Register - Clock Select
Definition in Ifx_MSC.ABC.B.CLKSEL. More...
|
| |
| enum | IfxMsc_CommandDataCommandRepetitionMode {
IfxMsc_CommandDataCommandRepetitionMode_disabled = 0,
IfxMsc_CommandDataCommandRepetitionMode_enabled = 1
} |
| | Downstream Control Enhanced Register - Command-Data-Command in Data Repetition Mode
Definition in Ifx_MSC.DSCE.B.CDCM. More...
|
| |
| enum | IfxMsc_CommandFrameInterrupt {
IfxMsc_CommandFrameInterrupt_disabled = 0,
IfxMsc_CommandFrameInterrupt_enabled = 1
} |
| | Interrupt Control Register - Command Frame Interrupt Enable
Definition in Ifx_MSC.ICR.B.ECIE. More...
|
| |
| enum | IfxMsc_CommandFrameInterruptNode {
IfxMsc_CommandFrameInterruptNode_SR0 = 0,
IfxMsc_CommandFrameInterruptNode_SR1,
IfxMsc_CommandFrameInterruptNode_SR2,
IfxMsc_CommandFrameInterruptNode_SR3
} |
| | Interrupt Control Register - Command Frame Interrupt Node Pointer
Definition in Ifx_MSC.ICR.B.ECIP. More...
|
| |
| enum | IfxMsc_CommandFrameLength {
IfxMsc_CommandFrameLength_0 = 0,
IfxMsc_CommandFrameLength_1 = 1,
IfxMsc_CommandFrameLength_2 = 2,
IfxMsc_CommandFrameLength_3,
IfxMsc_CommandFrameLength_4,
IfxMsc_CommandFrameLength_5,
IfxMsc_CommandFrameLength_6,
IfxMsc_CommandFrameLength_7,
IfxMsc_CommandFrameLength_8,
IfxMsc_CommandFrameLength_9,
IfxMsc_CommandFrameLength_10,
IfxMsc_CommandFrameLength_11,
IfxMsc_CommandFrameLength_12,
IfxMsc_CommandFrameLength_13,
IfxMsc_CommandFrameLength_14,
IfxMsc_CommandFrameLength_15,
IfxMsc_CommandFrameLength_16,
IfxMsc_CommandFrameLength_17 = 17,
IfxMsc_CommandFrameLength_18 = 18,
IfxMsc_CommandFrameLength_19,
IfxMsc_CommandFrameLength_20,
IfxMsc_CommandFrameLength_21,
IfxMsc_CommandFrameLength_22,
IfxMsc_CommandFrameLength_23,
IfxMsc_CommandFrameLength_24,
IfxMsc_CommandFrameLength_25,
IfxMsc_CommandFrameLength_26,
IfxMsc_CommandFrameLength_27,
IfxMsc_CommandFrameLength_28,
IfxMsc_CommandFrameLength_29,
IfxMsc_CommandFrameLength_30,
IfxMsc_CommandFrameLength_31,
IfxMsc_CommandFrameLength_32
} |
| | Number of Bits shifted at command frames
Definition in Ifx_MSC.DSC.B.NBC. More...
|
| |
| enum | IfxMsc_ControlFrameExtensionPassivePhaseLength {
IfxMsc_ControlFrameExtensionPassivePhaseLength_0 = 0,
IfxMsc_ControlFrameExtensionPassivePhaseLength_1,
IfxMsc_ControlFrameExtensionPassivePhaseLength_2,
IfxMsc_ControlFrameExtensionPassivePhaseLength_3,
IfxMsc_ControlFrameExtensionPassivePhaseLength_4,
IfxMsc_ControlFrameExtensionPassivePhaseLength_5,
IfxMsc_ControlFrameExtensionPassivePhaseLength_6,
IfxMsc_ControlFrameExtensionPassivePhaseLength_7,
IfxMsc_ControlFrameExtensionPassivePhaseLength_8,
IfxMsc_ControlFrameExtensionPassivePhaseLength_9,
IfxMsc_ControlFrameExtensionPassivePhaseLength_10,
IfxMsc_ControlFrameExtensionPassivePhaseLength_11,
IfxMsc_ControlFrameExtensionPassivePhaseLength_12,
IfxMsc_ControlFrameExtensionPassivePhaseLength_13,
IfxMsc_ControlFrameExtensionPassivePhaseLength_14,
IfxMsc_ControlFrameExtensionPassivePhaseLength_15,
IfxMsc_ControlFrameExtensionPassivePhaseLength_16,
IfxMsc_ControlFrameExtensionPassivePhaseLength_17,
IfxMsc_ControlFrameExtensionPassivePhaseLength_18,
IfxMsc_ControlFrameExtensionPassivePhaseLength_19,
IfxMsc_ControlFrameExtensionPassivePhaseLength_20,
IfxMsc_ControlFrameExtensionPassivePhaseLength_21,
IfxMsc_ControlFrameExtensionPassivePhaseLength_22,
IfxMsc_ControlFrameExtensionPassivePhaseLength_23,
IfxMsc_ControlFrameExtensionPassivePhaseLength_24,
IfxMsc_ControlFrameExtensionPassivePhaseLength_25,
IfxMsc_ControlFrameExtensionPassivePhaseLength_26,
IfxMsc_ControlFrameExtensionPassivePhaseLength_27,
IfxMsc_ControlFrameExtensionPassivePhaseLength_28,
IfxMsc_ControlFrameExtensionPassivePhaseLength_29,
IfxMsc_ControlFrameExtensionPassivePhaseLength_30,
IfxMsc_ControlFrameExtensionPassivePhaseLength_31,
IfxMsc_ControlFrameExtensionPassivePhaseLength_32,
IfxMsc_ControlFrameExtensionPassivePhaseLength_33,
IfxMsc_ControlFrameExtensionPassivePhaseLength_34,
IfxMsc_ControlFrameExtensionPassivePhaseLength_35,
IfxMsc_ControlFrameExtensionPassivePhaseLength_36,
IfxMsc_ControlFrameExtensionPassivePhaseLength_37,
IfxMsc_ControlFrameExtensionPassivePhaseLength_38,
IfxMsc_ControlFrameExtensionPassivePhaseLength_39,
IfxMsc_ControlFrameExtensionPassivePhaseLength_40,
IfxMsc_ControlFrameExtensionPassivePhaseLength_41,
IfxMsc_ControlFrameExtensionPassivePhaseLength_42,
IfxMsc_ControlFrameExtensionPassivePhaseLength_43,
IfxMsc_ControlFrameExtensionPassivePhaseLength_44,
IfxMsc_ControlFrameExtensionPassivePhaseLength_45,
IfxMsc_ControlFrameExtensionPassivePhaseLength_46,
IfxMsc_ControlFrameExtensionPassivePhaseLength_47,
IfxMsc_ControlFrameExtensionPassivePhaseLength_48,
IfxMsc_ControlFrameExtensionPassivePhaseLength_49,
IfxMsc_ControlFrameExtensionPassivePhaseLength_50,
IfxMsc_ControlFrameExtensionPassivePhaseLength_51,
IfxMsc_ControlFrameExtensionPassivePhaseLength_52,
IfxMsc_ControlFrameExtensionPassivePhaseLength_53,
IfxMsc_ControlFrameExtensionPassivePhaseLength_54,
IfxMsc_ControlFrameExtensionPassivePhaseLength_55,
IfxMsc_ControlFrameExtensionPassivePhaseLength_56,
IfxMsc_ControlFrameExtensionPassivePhaseLength_57,
IfxMsc_ControlFrameExtensionPassivePhaseLength_58,
IfxMsc_ControlFrameExtensionPassivePhaseLength_59,
IfxMsc_ControlFrameExtensionPassivePhaseLength_60,
IfxMsc_ControlFrameExtensionPassivePhaseLength_61,
IfxMsc_ControlFrameExtensionPassivePhaseLength_62,
IfxMsc_ControlFrameExtensionPassivePhaseLength_63
} |
| | Downstream Timing Extension Register - Passive Phase Length at Control Frames Extension
Definition in Ifx_MSC.DSTE.B.PPCE. More...
|
| |
| enum | IfxMsc_DataFrameExtensionPassivePhaseLength {
IfxMsc_DataFrameExtensionPassivePhaseLength_0 = 0,
IfxMsc_DataFrameExtensionPassivePhaseLength_1,
IfxMsc_DataFrameExtensionPassivePhaseLength_2,
IfxMsc_DataFrameExtensionPassivePhaseLength_3
} |
| | Downstream Timing Extension Register - Passive Phase Length at Data Frames Extension
Definition in Ifx_MSC.DSTE.B.PPDE. More...
|
| |
| enum | IfxMsc_DataFrameInterrupt {
IfxMsc_DataFrameInterrupt_disabled = 0,
IfxMsc_DataFrameInterrupt_atLastDataBit = 1,
IfxMsc_DataFrameInterrupt_atFirstDataBit = 2
} |
| | Interrupt Control Register - Data Frame Interrupt Enable
Definition in Ifx_MSC.ICR.B.EDIE. More...
|
| |
| enum | IfxMsc_DataFrameInterruptNode {
IfxMsc_DataFrameInterruptNode_SR0 = 0,
IfxMsc_DataFrameInterruptNode_SR1,
IfxMsc_DataFrameInterruptNode_SR2,
IfxMsc_DataFrameInterruptNode_SR3
} |
| | Interrupt Control Register - Data Frame Interrupt Node Pointer
Definition in Ifx_MSC.ICR.B.EDIP. More...
|
| |
| enum | IfxMsc_DataFrameLength {
IfxMsc_DataFrameLength_0 = 0,
IfxMsc_DataFrameLength_1 = 1,
IfxMsc_DataFrameLength_2 = 2,
IfxMsc_DataFrameLength_3,
IfxMsc_DataFrameLength_4,
IfxMsc_DataFrameLength_5,
IfxMsc_DataFrameLength_6,
IfxMsc_DataFrameLength_7,
IfxMsc_DataFrameLength_8,
IfxMsc_DataFrameLength_9,
IfxMsc_DataFrameLength_10,
IfxMsc_DataFrameLength_11,
IfxMsc_DataFrameLength_12,
IfxMsc_DataFrameLength_13,
IfxMsc_DataFrameLength_14,
IfxMsc_DataFrameLength_15,
IfxMsc_DataFrameLength_16
} |
| | Number of SRx[] (x->SRL/SRH) Bits Shifted at Data Frames
Definition in Ifx_MSC.DSC.B.NDBH and Ifx_MSC.DSC.B.NDBL. More...
|
| |
| enum | IfxMsc_DataFramePassivePhaseLength {
IfxMsc_DataFramePassivePhaseLength_2 = 2,
IfxMsc_DataFramePassivePhaseLength_3,
IfxMsc_DataFramePassivePhaseLength_4,
IfxMsc_DataFramePassivePhaseLength_5,
IfxMsc_DataFramePassivePhaseLength_6,
IfxMsc_DataFramePassivePhaseLength_7,
IfxMsc_DataFramePassivePhaseLength_8,
IfxMsc_DataFramePassivePhaseLength_9,
IfxMsc_DataFramePassivePhaseLength_10,
IfxMsc_DataFramePassivePhaseLength_11,
IfxMsc_DataFramePassivePhaseLength_12,
IfxMsc_DataFramePassivePhaseLength_13,
IfxMsc_DataFramePassivePhaseLength_14,
IfxMsc_DataFramePassivePhaseLength_15,
IfxMsc_DataFramePassivePhaseLength_16,
IfxMsc_DataFramePassivePhaseLength_17,
IfxMsc_DataFramePassivePhaseLength_18,
IfxMsc_DataFramePassivePhaseLength_19,
IfxMsc_DataFramePassivePhaseLength_20,
IfxMsc_DataFramePassivePhaseLength_21,
IfxMsc_DataFramePassivePhaseLength_22,
IfxMsc_DataFramePassivePhaseLength_23,
IfxMsc_DataFramePassivePhaseLength_24,
IfxMsc_DataFramePassivePhaseLength_25,
IfxMsc_DataFramePassivePhaseLength_26,
IfxMsc_DataFramePassivePhaseLength_27,
IfxMsc_DataFramePassivePhaseLength_28,
IfxMsc_DataFramePassivePhaseLength_29,
IfxMsc_DataFramePassivePhaseLength_30,
IfxMsc_DataFramePassivePhaseLength_31,
IfxMsc_DataFramePassivePhaseLength_32
} |
| | Passive Phase Length at Data Frames
Definition in Ifx_MSC.DSC.B.PPD. More...
|
| |
| enum | IfxMsc_DividerMode {
IfxMsc_DividerMode_normal = 1,
IfxMsc_DividerMode_fractional = 2
} |
| | Divider mode. More...
|
| |
| enum | IfxMsc_EmergencyStop {
IfxMsc_EmergencyStop_disabled = 0,
IfxMsc_EmergencyStop_enabled = 1
} |
| | Emergency Stop Register - Emergency stop feature Enable or Disable - SRL and SRH
Definition in Ifx_MSC.ESR. More...
|
| |
| enum | IfxMsc_Extension {
IfxMsc_Extension_disabled = 0,
IfxMsc_Extension_enabled = 1
} |
| | Downstream Control Enhanced Register - Extension Enable
Definition in Ifx_MSC.DSCE.B.NDBLE. More...
|
| |
| enum | IfxMsc_ExternalBitInjectionPosition {
IfxMsc_ExternalBitInjectionPosition_0 = 0,
IfxMsc_ExternalBitInjectionPosition_1,
IfxMsc_ExternalBitInjectionPosition_2,
IfxMsc_ExternalBitInjectionPosition_3,
IfxMsc_ExternalBitInjectionPosition_4,
IfxMsc_ExternalBitInjectionPosition_5,
IfxMsc_ExternalBitInjectionPosition_6,
IfxMsc_ExternalBitInjectionPosition_7,
IfxMsc_ExternalBitInjectionPosition_8,
IfxMsc_ExternalBitInjectionPosition_9,
IfxMsc_ExternalBitInjectionPosition_10,
IfxMsc_ExternalBitInjectionPosition_11,
IfxMsc_ExternalBitInjectionPosition_12,
IfxMsc_ExternalBitInjectionPosition_13,
IfxMsc_ExternalBitInjectionPosition_14,
IfxMsc_ExternalBitInjectionPosition_15,
IfxMsc_ExternalBitInjectionPosition_16,
IfxMsc_ExternalBitInjectionPosition_17,
IfxMsc_ExternalBitInjectionPosition_18,
IfxMsc_ExternalBitInjectionPosition_19,
IfxMsc_ExternalBitInjectionPosition_20,
IfxMsc_ExternalBitInjectionPosition_21,
IfxMsc_ExternalBitInjectionPosition_22,
IfxMsc_ExternalBitInjectionPosition_23,
IfxMsc_ExternalBitInjectionPosition_24,
IfxMsc_ExternalBitInjectionPosition_25,
IfxMsc_ExternalBitInjectionPosition_26,
IfxMsc_ExternalBitInjectionPosition_27,
IfxMsc_ExternalBitInjectionPosition_28,
IfxMsc_ExternalBitInjectionPosition_29,
IfxMsc_ExternalBitInjectionPosition_30,
IfxMsc_ExternalBitInjectionPosition_31,
IfxMsc_ExternalBitInjectionPosition_32,
IfxMsc_ExternalBitInjectionPosition_33,
IfxMsc_ExternalBitInjectionPosition_34,
IfxMsc_ExternalBitInjectionPosition_35,
IfxMsc_ExternalBitInjectionPosition_36,
IfxMsc_ExternalBitInjectionPosition_37,
IfxMsc_ExternalBitInjectionPosition_38,
IfxMsc_ExternalBitInjectionPosition_39,
IfxMsc_ExternalBitInjectionPosition_40,
IfxMsc_ExternalBitInjectionPosition_41,
IfxMsc_ExternalBitInjectionPosition_42,
IfxMsc_ExternalBitInjectionPosition_43,
IfxMsc_ExternalBitInjectionPosition_44,
IfxMsc_ExternalBitInjectionPosition_45,
IfxMsc_ExternalBitInjectionPosition_46,
IfxMsc_ExternalBitInjectionPosition_47,
IfxMsc_ExternalBitInjectionPosition_48,
IfxMsc_ExternalBitInjectionPosition_49,
IfxMsc_ExternalBitInjectionPosition_50,
IfxMsc_ExternalBitInjectionPosition_51,
IfxMsc_ExternalBitInjectionPosition_52,
IfxMsc_ExternalBitInjectionPosition_53,
IfxMsc_ExternalBitInjectionPosition_54,
IfxMsc_ExternalBitInjectionPosition_55,
IfxMsc_ExternalBitInjectionPosition_56,
IfxMsc_ExternalBitInjectionPosition_57,
IfxMsc_ExternalBitInjectionPosition_58,
IfxMsc_ExternalBitInjectionPosition_59,
IfxMsc_ExternalBitInjectionPosition_60,
IfxMsc_ExternalBitInjectionPosition_61,
IfxMsc_ExternalBitInjectionPosition_62,
IfxMsc_ExternalBitInjectionPosition_63
} |
| | Downstream Control Enhanced Register - Injection Position of the Pin 0 and 1 Signal
Definition in Ifx_MSC.DSCE.B.INJPOSP0 and Ifx_MSC.DSCE.B.INJPOSP1. More...
|
| |
| enum | IfxMsc_ExternalSignalInjection {
IfxMsc_ExternalSignalInjection_disabled = 0,
IfxMsc_ExternalSignalInjection_enabled = 1
} |
| | Downstream Control Enhanced Register - Injection Enable of the Pin 0 and 1 Signal
Definition in Ifx_MSC.DSCE.B.INJENP0 and Ifx_MSC.DSCE.B.INJENP1. More...
|
| |
| enum | IfxMsc_FclClockControlEnabled {
IfxMsc_FclClockControlEnabled_activePhaseOnly = 0,
IfxMsc_FclClockControlEnabled_always = 1
} |
| | Output Control Register - Clock Control
Definition in Ifx_MSC.OCR.B.CLKCTRL. More...
|
| |
| enum | IfxMsc_FclLinePolarity {
IfxMsc_FclLinePolarity_nonInverted = 0,
IfxMsc_FclLinePolarity_inverted = 1
} |
| | Output Control Register - FCLP Line Polarity
Definition in Ifx_MSC.OCR.B.CLP. More...
|
| |
| enum | IfxMsc_HardwareClock {
IfxMsc_HardwareClock_disabled = 0,
IfxMsc_HardwareClock_enabled = 1
} |
| | Enable hardware clock control. More...
|
| |
| enum | IfxMsc_ModuleSuspendRequestBit {
IfxMsc_ModuleSuspendRequestBit_noSuspend = 0,
IfxMsc_ModuleSuspendRequestBit_hardSuspend = 1,
IfxMsc_ModuleSuspendRequestBit_softSuspend = 2
} |
| | OCDS Control and Status - OCDS Suspend Control Definition in Ifx_MSC.OCS.B.SUS. More...
|
| |
| enum | IfxMsc_MsbBitDataExtension {
IfxMsc_MsbBitDataExtension_notPresent = 0,
IfxMsc_MsbBitDataExtension_present = 1
} |
| | Downstream Control Enhanced Register - Number of SRL/SRH Bits Shifted at Data Frames Extension (NDBL/NDBH)
Definition in Ifx_MSC.DSCE.B.NDBLE and Ifx_MSC.DSCE.B.NDBHE. More...
|
| |
| enum | IfxMsc_NDividerAbra {
IfxMsc_NDividerAbra_1 = 0,
IfxMsc_NDividerAbra_2,
IfxMsc_NDividerAbra_3,
IfxMsc_NDividerAbra_4,
IfxMsc_NDividerAbra_5,
IfxMsc_NDividerAbra_6,
IfxMsc_NDividerAbra_7,
IfxMsc_NDividerAbra_8
} |
| | Asynchronous Block Configuration Register - N Divider ABRA
Definition in Ifx_MSC.ABC.B.NDA. More...
|
| |
| enum | IfxMsc_NDividerDownstream {
IfxMsc_NDividerDownstream_1 = 0,
IfxMsc_NDividerDownstream_2,
IfxMsc_NDividerDownstream_3,
IfxMsc_NDividerDownstream_4,
IfxMsc_NDividerDownstream_5,
IfxMsc_NDividerDownstream_6,
IfxMsc_NDividerDownstream_7,
IfxMsc_NDividerDownstream_8,
IfxMsc_NDividerDownstream_9,
IfxMsc_NDividerDownstream_10,
IfxMsc_NDividerDownstream_11,
IfxMsc_NDividerDownstream_12,
IfxMsc_NDividerDownstream_13,
IfxMsc_NDividerDownstream_14,
IfxMsc_NDividerDownstream_15,
IfxMsc_NDividerDownstream_16
} |
| | Downstream Timing Extension Register - N Divider Downstream
Definition in Ifx_MSC.DSTE.B.NDD. More...
|
| |
| enum | IfxMsc_OverflowInterrupt {
IfxMsc_OverflowInterrupt_disabled = 0,
IfxMsc_OverflowInterrupt_enabled = 1
} |
| | Asynchronous Block Configuration Register - Overflow Interrupt Enable
Definition in Ifx_MSC.ABC.B.OIE. More...
|
| |
| enum | IfxMsc_OverflowInterruptNode {
IfxMsc_OverflowInterruptNode_SR0 = 0,
IfxMsc_OverflowInterruptNode_SR1,
IfxMsc_OverflowInterruptNode_SR2,
IfxMsc_OverflowInterruptNode_SR3,
IfxMsc_OverflowInterruptNode_SR4
} |
| | Asynchronous Block Configuration Register - Overflow Interrupt Node Pointer
Definition in Ifx_MSC.ABC.B.OIP. More...
|
| |
| enum | IfxMsc_Parity {
IfxMsc_Parity_even = 0,
IfxMsc_Parity_odd = 1
} |
| | Parity Mode
Definition in Ifx_MSC.USR.B.PCT. More...
|
| |
| enum | IfxMsc_PassiveTimeFrameCount {
IfxMsc_PassiveTimeFrameCount_0 = 0,
IfxMsc_PassiveTimeFrameCount_1 = 1,
IfxMsc_PassiveTimeFrameCount_2,
IfxMsc_PassiveTimeFrameCount_3,
IfxMsc_PassiveTimeFrameCount_4,
IfxMsc_PassiveTimeFrameCount_5,
IfxMsc_PassiveTimeFrameCount_6,
IfxMsc_PassiveTimeFrameCount_7,
IfxMsc_PassiveTimeFrameCount_8,
IfxMsc_PassiveTimeFrameCount_9,
IfxMsc_PassiveTimeFrameCount_10,
IfxMsc_PassiveTimeFrameCount_11,
IfxMsc_PassiveTimeFrameCount_12,
IfxMsc_PassiveTimeFrameCount_13,
IfxMsc_PassiveTimeFrameCount_14,
IfxMsc_PassiveTimeFrameCount_15
} |
| | Downstream Status Register - Number Of Passive Time Frames
Definition in Ifx_MSC.DSS.B.NPTF. More...
|
| |
| enum | IfxMsc_ReceiveDataInterrupt {
IfxMsc_ReceiveDataInterrupt_disabled = 0,
IfxMsc_ReceiveDataInterrupt_onDataReceive = 1,
IfxMsc_ReceiveDataInterrupt_onRdieSet = 2,
IfxMsc_ReceiveDataInterrupt_onDataReceiveInUd3 = 3
} |
| | Interrupt Control Register - Receive Data Interrupt Enable
Definition in Ifx_MSC.ICR.B.RDIE. More...
|
| |
| enum | IfxMsc_ReceiveDataInterruptNode {
IfxMsc_ReceiveDataInterruptNode_SR0 = 0,
IfxMsc_ReceiveDataInterruptNode_SR1,
IfxMsc_ReceiveDataInterruptNode_SR2,
IfxMsc_ReceiveDataInterruptNode_SR3
} |
| | Interrupt Control Register - Receive Data Interrupt Pointer
Definition in Ifx_MSC.ICR.B.RDIP. More...
|
| |
| enum | IfxMsc_SdiLinePolarity {
IfxMsc_SdiLinePolarity_likeSi = 0,
IfxMsc_SdiLinePolarity_invertedSi = 1
} |
| | Output Control Register - SDI Line Polarity
Definition in Ifx_MSC.OCR.B.ILP. More...
|
| |
| enum | IfxMsc_SerialDataInput {
IfxMsc_SerialDataInput_0 = 0,
IfxMsc_SerialDataInput_1,
IfxMsc_SerialDataInput_2,
IfxMsc_SerialDataInput_3,
IfxMsc_SerialDataInput_4,
IfxMsc_SerialDataInput_5,
IfxMsc_SerialDataInput_6,
IfxMsc_SerialDataInput_7
} |
| | Output Control Register - Serial Data Input Selection
Definition in Ifx_MSC.OCR.B.SDISEL. More...
|
| |
| enum | IfxMsc_ServiceRequestDelay {
IfxMsc_ServiceRequestDelay_noDelay = 0,
IfxMsc_ServiceRequestDelay_1bit = 1
} |
| | Service Request Delay
Definition in Ifx_MSC.USR.B.SRDC. More...
|
| |
| enum | IfxMsc_ShiftClockPhaseDuration {
IfxMsc_ShiftClockPhaseDuration_1 = 0,
IfxMsc_ShiftClockPhaseDuration_2,
IfxMsc_ShiftClockPhaseDuration_3,
IfxMsc_ShiftClockPhaseDuration_4,
IfxMsc_ShiftClockPhaseDuration_5,
IfxMsc_ShiftClockPhaseDuration_6,
IfxMsc_ShiftClockPhaseDuration_7,
IfxMsc_ShiftClockPhaseDuration_8,
IfxMsc_ShiftClockPhaseDuration_9,
IfxMsc_ShiftClockPhaseDuration_10,
IfxMsc_ShiftClockPhaseDuration_11,
IfxMsc_ShiftClockPhaseDuration_12,
IfxMsc_ShiftClockPhaseDuration_13,
IfxMsc_ShiftClockPhaseDuration_14,
IfxMsc_ShiftClockPhaseDuration_15,
IfxMsc_ShiftClockPhaseDuration_16
} |
| | Asynchronous Block Configuration Register - Duration of the Low/High Phase of the Shift Clock
Definition in Ifx_MSC.ABC.B.LOW and Ifx_MSC.ABC.B.HIGH. More...
|
| |
| enum | IfxMsc_SleepMode {
IfxMsc_SleepMode_enable = 0,
IfxMsc_SleepMode_disable = 1
} |
| | Enable/disable the sensitivity of the module to sleep signal
Definition in Ifx_MSC.CLC.B.EDIS. More...
|
| |
| enum | IfxMsc_SoLinePolarity {
IfxMsc_SoLinePolarity_nonInverted = 0,
IfxMsc_SoLinePolarity_inverted = 1
} |
| | Output Control Register - SOP Line Polarity
Definition in Ifx_MSC.OCR.B.SLP. More...
|
| |
| enum | IfxMsc_Source {
IfxMsc_Source_downstreamDataRegister = 0,
IfxMsc_Source_alternateInputLine = 2,
IfxMsc_Source_alternateInputLineInverted = 3
} |
| | Downstream Select Data Source Low Register - Select Source for - SRL and SRHNumber Of Passive Time Frames
Definition in Ifx_MSC.DSDSL and Ifx_MSC.DSDSH. More...
|
| |
| enum | IfxMsc_Target {
IfxMsc_Target_en0 = 0,
IfxMsc_Target_en1,
IfxMsc_Target_en2,
IfxMsc_Target_en3
} |
| | Msc Targets - use as chip enable selection for ENH, ENL and ENC. More...
|
| |
| enum | IfxMsc_TimeFrameInterrupt {
IfxMsc_TimeFrameInterrupt_disabled = 0,
IfxMsc_TimeFrameInterrupt_enabled = 1
} |
| | Interrupt Control Register - Time Frame Interrupt Enable
Definition in Ifx_MSC.ICR.B.TFIE. More...
|
| |
| enum | IfxMsc_TimeFrameInterruptNode {
IfxMsc_TimeFrameInterruptNode_SR0 = 0,
IfxMsc_TimeFrameInterruptNode_SR1,
IfxMsc_TimeFrameInterruptNode_SR2,
IfxMsc_TimeFrameInterruptNode_SR3
} |
| | Interrupt Control Register - Time Frame Interrupt Pointer
Definition in Ifx_MSC.ICR.B.TFIP. More...
|
| |
| enum | IfxMsc_TransmissionMode {
IfxMsc_TransmissionMode_triggered = 0,
IfxMsc_TransmissionMode_dataRepetition = 1
} |
| | Downstream Channel Transmission Mode
Definition in Ifx_MSC.DSC.B.TM. More...
|
| |
| enum | IfxMsc_UnderflowInterrupt {
IfxMsc_UnderflowInterrupt_disabled = 0,
IfxMsc_UnderflowInterrupt_enabled = 1
} |
| | Asynchronous Block Configuration Register - Underflow Interrupt Enable
Definition in Ifx_MSC.ABC.B.UIE. More...
|
| |
| enum | IfxMsc_UnderflowInterruptNode {
IfxMsc_UnderflowInterruptNode_SR0 = 0,
IfxMsc_UnderflowInterruptNode_SR1,
IfxMsc_UnderflowInterruptNode_SR2,
IfxMsc_UnderflowInterruptNode_SR3,
IfxMsc_UnderflowInterruptNode_SR4
} |
| | Asynchronous Block Configuration Register - Underflow Interrupt Node Pointer
Definition in Ifx_MSC.ABC.B.UIP. More...
|
| |
| enum | IfxMsc_UpstreamChannelFrameType {
IfxMsc_UpstreamChannelFrameType_12bit = 0,
IfxMsc_UpstreamChannelFrameType_16bit = 1
} |
| | Channel Frame Type
Definition in Ifx_MSC.USR.B.UFT. More...
|
| |
| enum | IfxMsc_UpstreamChannelReceivingRate {
IfxMsc_UpstreamChannelReceivingRate_disabled = 0,
IfxMsc_UpstreamChannelReceivingRate_4 = 1,
IfxMsc_UpstreamChannelReceivingRate_8 = 2,
IfxMsc_UpstreamChannelReceivingRate_16 = 3,
IfxMsc_UpstreamChannelReceivingRate_32 = 4,
IfxMsc_UpstreamChannelReceivingRate_64 = 5,
IfxMsc_UpstreamChannelReceivingRate_128 = 6,
IfxMsc_UpstreamChannelReceivingRate_256 = 7
} |
| | Upstream Receiving Rate
Definition in Ifx_MSC.USR.B.URR. More...
|
| |
| enum | IfxMsc_UpstreamTimeoutInterrupt {
IfxMsc_UpstreamTimeoutInterrupt_disabled = 0,
IfxMsc_UpstreamTimeoutInterrupt_enabled = 1
} |
| | Upstream Control Enhanced Register 1 - Upstream Timeout Interrupt Enable
Definition in Ifx_MSC.USCE.B.USTOEN. More...
|
| |
| enum | IfxMsc_UpstreamTimeoutInterruptNode {
IfxMsc_UpstreamTimeoutInterruptNode_SR0 = 0,
IfxMsc_UpstreamTimeoutInterruptNode_SR1,
IfxMsc_UpstreamTimeoutInterruptNode_SR2,
IfxMsc_UpstreamTimeoutInterruptNode_SR3
} |
| | Upstream Control Enhanced Register 1 - Upstream Timeout Interrupt Node Pointer
Definition in Ifx_MSC.USCE.B.USTOIP. More...
|
| |
| enum | IfxMsc_UpstreamTimeoutPrescaler {
IfxMsc_UpstreamTimeoutPrescaler_1 = 0,
IfxMsc_UpstreamTimeoutPrescaler_2 = 1,
IfxMsc_UpstreamTimeoutPrescaler_4 = 2,
IfxMsc_UpstreamTimeoutPrescaler_8 = 3,
IfxMsc_UpstreamTimeoutPrescaler_16 = 4,
IfxMsc_UpstreamTimeoutPrescaler_32 = 5,
IfxMsc_UpstreamTimeoutPrescaler_64 = 6,
IfxMsc_UpstreamTimeoutPrescaler_128 = 7,
IfxMsc_UpstreamTimeoutPrescaler_256 = 8,
IfxMsc_UpstreamTimeoutPrescaler_512 = 9,
IfxMsc_UpstreamTimeoutPrescaler_1024 = 10,
IfxMsc_UpstreamTimeoutPrescaler_2048 = 11,
IfxMsc_UpstreamTimeoutPrescaler_4096 = 12,
IfxMsc_UpstreamTimeoutPrescaler_8192 = 13,
IfxMsc_UpstreamTimeoutPrescaler_16384 = 14,
IfxMsc_UpstreamTimeoutPrescaler_32768 = 15
} |
| | Upstream Control Enhanced Register 1 - Upstream Timeout Prescaler
Definition in Ifx_MSC.USCE.B.USTOPRE. More...
|
| |
| enum | IfxMsc_UpstreamTimeoutValue {
IfxMsc_UpstreamTimeoutValue_1 = 0,
IfxMsc_UpstreamTimeoutValue_2,
IfxMsc_UpstreamTimeoutValue_3,
IfxMsc_UpstreamTimeoutValue_4,
IfxMsc_UpstreamTimeoutValue_5,
IfxMsc_UpstreamTimeoutValue_6,
IfxMsc_UpstreamTimeoutValue_7,
IfxMsc_UpstreamTimeoutValue_8,
IfxMsc_UpstreamTimeoutValue_9,
IfxMsc_UpstreamTimeoutValue_10,
IfxMsc_UpstreamTimeoutValue_11,
IfxMsc_UpstreamTimeoutValue_12,
IfxMsc_UpstreamTimeoutValue_13,
IfxMsc_UpstreamTimeoutValue_14,
IfxMsc_UpstreamTimeoutValue_15,
IfxMsc_UpstreamTimeoutValue_16
} |
| | Upstream Control Enhanced Register 1 - Upstream Timeout Value
Definition in Ifx_MSC.USCE.B.USTOVAL. More...
|
| |
|
| IFX_INLINE void | IfxMsc_clearAbraOverflowFlag (Ifx_MSC *msc) |
| | Clear ABRA overflow flag. More...
|
| |
| IFX_INLINE void | IfxMsc_clearAbraUnderflowFlag (Ifx_MSC *msc) |
| | Clear ABRA underflow flag. More...
|
| |
| IFX_INLINE void | IfxMsc_clearUpstreamTimeout (Ifx_MSC *msc) |
| | Clear Upstream timeout. More...
|
| |
| IFX_INLINE void | IfxMsc_clearUpstreamValidFlag (Ifx_MSC *msc, uint8 upstreamIdx) |
| | Clear the valid flag. More...
|
| |
| IFX_INLINE boolean | IfxMsc_getUpstreamValidFlag (Ifx_MSC *msc, uint8 upstreamIdx) |
| | Get the status of the valid flag. More...
|
| |
| IFX_INLINE void | IfxMsc_setCommandTarget (Ifx_MSC *msc, IfxMsc_Target enX) |
| | Select the target for command phase. More...
|
| |
| IFX_INLINE void | IfxMsc_setDataHighTarget (Ifx_MSC *msc, IfxMsc_Target enX) |
| | Select the target for data high phase. More...
|
| |
| IFX_INLINE void | IfxMsc_setDataLowTarget (Ifx_MSC *msc, IfxMsc_Target enX) |
| | Select the target for data low phase. More...
|
| |
| IFX_INLINE uint16 | IfxMsc_getData (Ifx_MSC *msc, uint8 upstreamIdx) |
| | Get the upstream data from upstream data register. More...
|
| |
| IFX_INLINE IfxMsc_Target | IfxMsc_getDataHighTarget (Ifx_MSC *msc) |
| | Get the selected target during high phase. More...
|
| |
| IFX_INLINE IfxMsc_Target | IfxMsc_getDataLowTarget (Ifx_MSC *msc) |
| | Get the selected target during low phase. More...
|
| |
| IFX_EXTERN void | IfxMsc_enableModule (Ifx_MSC *msc) |
| | Enable MSC kernel. More...
|
| |
| IFX_EXTERN void | IfxMsc_clearReset (Ifx_MSC *msc) |
| | Clear reset bit of MSC kernel. More...
|
| |
| IFX_EXTERN void | IfxMsc_resetModule (Ifx_MSC *msc) |
| | Reset MSC kernel. More...
|
| |
| IFX_EXTERN uint32 | IfxMsc_downstreamAbraBaudCalculator (uint32 baud) |
| | Get the NDD value for the supplied baud rate when when ABRA block is enabled. More...
|
| |
| IFX_EXTERN uint64 | IfxMsc_upstreamFractionalBaudCalculator (Ifx_MSC *msc, uint32 baud) |
| | Get the step value for the supplied baud rate when divider mode is fractional. More...
|
| |
| IFX_EXTERN uint32 | IfxMsc_upstreamNormalBaudCalculator (Ifx_MSC *msc, uint32 baud) |
| | Get the step value for the supplied baud rate when divider mode is normal. More...
|
| |
| IFX_INLINE void | IfxMsc_initEnPin (const IfxMsc_En_Out *en, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver) |
| | Initializes a EN output. More...
|
| |
| IFX_INLINE void | IfxMsc_initFclnPin (const IfxMsc_Fcln_Out *fcln, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver) |
| | Initializes a FCLN output. More...
|
| |
| IFX_INLINE void | IfxMsc_initFclpPin (const IfxMsc_Fclp_Out *fclp, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver) |
| | Initializes a FCLP output. More...
|
| |
| IFX_INLINE void | IfxMsc_initInjPin (const IfxMsc_Inj_In *inj, IfxPort_InputMode pinMode) |
| | Initializes a INJ input. More...
|
| |
| IFX_INLINE void | IfxMsc_initSdiPin (const IfxMsc_Sdi_In *sdi, IfxPort_InputMode pinMode) |
| | Initializes a SDI input. More...
|
| |
| IFX_INLINE void | IfxMsc_initSonPin (const IfxMsc_Son_Out *son, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver) |
| | Initializes a SON output. More...
|
| |
| IFX_INLINE void | IfxMsc_initSopPin (const IfxMsc_Sop_Out *sop, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver) |
| | Initializes a SOP output. More...
|
| |
| IFX_INLINE void | IfxMsc_setSleepMode (Ifx_MSC *msc, IfxMsc_SleepMode mode) |
| | Sets the sensitivity of the module to sleep signal. More...
|
| |
| IFX_EXTERN void | IfxMsc_clearDataFrameInterruptFlag (Ifx_MSC *msc) |
| | clear data frame interrupt flag More...
|
| |
| IFX_EXTERN boolean | IfxMsc_getActiveDataFrameStatus (Ifx_MSC *msc) |
| | get the status of the active data frame More...
|
| |
| IFX_EXTERN boolean | IfxMsc_getDataFrameInterruptFlag (Ifx_MSC *msc) |
| | get the status of the data frame interrupt flag More...
|
| |
MSC basic functionality.
- Version
- iLLD_1_0_0_11_0
- Copyright
- Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
IMPORTANT NOTICE
Infineon Technologies AG (Infineon) is supplying this file for use exclusively with Infineon's microcontroller products. This file can be freely distributed within development tools that are supporting such microcontroller products.
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Definition in file IfxMsc.h.
1.8.4