iLLD_TC27xD  1.0
IfxCpu_Intrinsics.h
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1 /**
2  * \file IfxCpu_Intrinsics.h
3  * \ingroup IfxLld_Cpu_Intrinsics Intrinsics
4  *
5  * \version iLLD_1_0_0_11_0
6  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  * \defgroup IfxLld_Cpu_Intrinsics Intrinsics
24  * \ingroup IfxLld_Cpu_Std
25  *
26  */
27 #ifndef IFXCPU_INTRINSICS_H
28 #define IFXCPU_INTRINSICS_H
29 /******************************************************************************/
30 #include "Ifx_Types.h"
31 
32 #if defined(__DCC__)
33 #include "IfxCpu_IntrinsicsDcc.h"
34 
35 #elif defined(__GNUC__)
36 #include "IfxCpu_IntrinsicsGnuc.h"
37 
38 #elif defined(__TASKING__)
39 #include "IfxCpu_IntrinsicsTasking.h"
40 
41 #else
42 #error Compiler unsupported
43 #endif
44 
45 #define IFX_ALIGN_8 (1) // Align on 8 bit Boundary
46 #define IFX_ALIGN_16 (2) // Align on 16 bit Boundary
47 #define IFX_ALIGN_32 (4) // Align on 32 bit Boundary
48 #define IFX_ALIGN_64 (8) // Align on 64 bit Boundary
49 #define IFX_ALIGN_256 (32) // Align on 256 bit Boundary
50 
51 #define Ifx_AlignOn256(Size) ((((Size) + (IFX_ALIGN_256 - 1)) & (~(IFX_ALIGN_256 - 1))))
52 #define Ifx_AlignOn64(Size) ((((Size) + (IFX_ALIGN_64 - 1)) & (~(IFX_ALIGN_64 - 1))))
53 #define Ifx_AlignOn32(Size) ((((Size) + (IFX_ALIGN_32 - 1)) & (~(IFX_ALIGN_32 - 1))))
54 #define Ifx_AlignOn16(Size) ((((Size) + (IFX_ALIGN_16 - 1)) & (~(IFX_ALIGN_16 - 1))))
55 #define Ifx_AlignOn8(Size) ((((Size) + (IFX_ALIGN_8 - 1)) & (~(IFX_ALIGN_8 - 1))))
56 
57 #define Ifx_COUNTOF(x) (sizeof(x) / sizeof(x[0]))
58 
59 //______________________________________________________________________________
60 
61 /** Convert context pointer to address pointer
62  * \param[in] cx context pointer
63  * \return address pointer
64  */
65 IFX_INLINE void *__cx_to_addr(uint32 cx)
66 {
67  uint32 seg_nr = __extru(cx, 16, 4);
68  return (void *)__insert(seg_nr << 28, cx, 6, 16);
69 }
70 
71 
72 /** Convert address pointer to context pointer
73  * \param[in] addr address pointer
74  * \return context pointer
75  */
76 IFX_INLINE uint32 __addr_to_cx(void *addr)
77 {
78  uint32 seg_nr, seg_idx;
79  seg_nr = __extru((int)addr, 28, 4) << 16;
80  seg_idx = __extru((int)addr, 6, 16);
81  return seg_nr | seg_idx;
82 }
83 
84 
85 /******************************************************************************/
86 IFX_INLINE void __ldmst_c(volatile void *address, unsigned mask, unsigned value)
87 {
88  *(volatile uint32 *)address = (*(volatile uint32 *)address & ~(mask)) | (mask & value);
89 }
90 
91 
92 /** 32bit load operation
93  */
94 IFX_INLINE uint32 __ld32(void *addr)
95 {
96  return *(volatile uint32 *)addr;
97 }
98 
99 
100 /** 32bit store operation
101  */
102 IFX_INLINE void __st32(void *addr, uint32 value)
103 {
104  *(volatile uint32 *)addr = value;
105 }
106 
107 
108 /** 64bit load operation
109  */
110 IFX_INLINE uint64 __ld64(void *addr)
111 {
112  return *(volatile uint64 *)addr;
113 }
114 
115 
116 /** 64bit store operation
117  */
118 IFX_INLINE void __st64(void *addr, uint64 value)
119 {
120  *(volatile uint64 *)addr = value;
121 }
122 
123 
124 /** 64bit load operation which returns the lower and upper 32bit word
125  */
126 IFX_INLINE void __ld64_lu(void *addr, uint32 *valueLower, uint32 *valueUpper)
127 {
128  register uint64 value;
129  value = __ld64(addr);
130  *valueLower = (uint32)value;
131  *valueUpper = (uint32)(value >> 32);
132 }
133 
134 
135 /** 64bit store operation which stores a lower and upper 32bit word
136  */
137 IFX_INLINE void __st64_lu(void *addr, uint32 valueLower, uint32 valueUpper)
138 {
139  register uint64 value = ((uint64)valueUpper << 32) | valueLower;
140  __st64(addr, value);
141 }
142 
143 
144 #define IFX_VECTOR_CPU0 (0)
145 #define IFX_VECTOR_CPU1 (1)
146 #define IFX_VECTOR_CPU2 (2)
147 #define IFX_VECTOR_CPU3 (3)
148 #define IFX_VECTOR_CPU4 (4)
149 #define IFX_VECTOR_CPU5 (5)
150 /******************************************************************************/
151 #endif /* IFXCPU_INTRINSICS_H */