iLLD_TC27xD  1.0
IfxMsc.h
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1 /**
2  * \file IfxMsc.h
3  * \brief MSC basic functionality
4  * \ingroup IfxLld_Msc
5  *
6  * \version iLLD_1_0_0_11_0
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Msc_Std_Enum Enumerations
25  * \ingroup IfxLld_Msc_Std
26  * \defgroup IfxLld_Msc_Std_Config_Flags Configure Flags
27  * \ingroup IfxLld_Msc_Std
28  * \defgroup IfxLld_Msc_Std_Set_Command_Target Set Command Target
29  * \ingroup IfxLld_Msc_Std
30  * \defgroup IfxLld_Msc_Std_Set_Data Set Data
31  * \ingroup IfxLld_Msc_Std
32  * \defgroup IfxLld_Msc_Std_Get_Data Get Data
33  * \ingroup IfxLld_Msc_Std
34  * \defgroup IfxLld_Msc_Std_Enable_Module Enable Module
35  * \ingroup IfxLld_Msc_Std
36  * \defgroup IfxLld_Msc_Std_Reset_Module Reset Module
37  * \ingroup IfxLld_Msc_Std
38  * \defgroup IfxLld_Msc_Std_Baud_Calculator Baud Calculator
39  * \ingroup IfxLld_Msc_Std
40  * \defgroup IfxLld_Msc_Std_IO IO Pin Configuration Functions
41  * \ingroup IfxLld_Msc_Std
42  */
43 
44 #ifndef IFXMSC_H
45 #define IFXMSC_H 1
46 
47 /******************************************************************************/
48 /*----------------------------------Includes----------------------------------*/
49 /******************************************************************************/
50 
51 #include "_Impl/IfxMsc_cfg.h"
52 #include "Scu/Std/IfxScuCcu.h"
53 #include "Scu/Std/IfxScuWdt.h"
54 #include "_PinMap/IfxMsc_PinMap.h"
55 #include "Cpu/Std/IfxCpu_Intrinsics.h"
56 
57 /******************************************************************************/
58 /*--------------------------------Enumerations--------------------------------*/
59 /******************************************************************************/
60 
61 /** \addtogroup IfxLld_Msc_Std_Enum
62  * \{ */
63 /** \brief Enable SRL/SRH Active Phase Selection Bit\n
64  * Definition in Ifx_MSC.DSC.B.ENSELH and Ifx_MSC.DSC.B.ENSELL
65  */
66 typedef enum
67 {
68  IfxMsc_ActivePhaseSelection_none = 0, /**< \brief No selection bit inserted */
69  IfxMsc_ActivePhaseSelection_lowLevel = 1 /**< \brief Low level selection bit inserted */
70 } IfxMsc_ActivePhaseSelection;
71 
72 /** \brief Asynchronous Block Configuration Register - Asynchronous Block Bypass\n
73  * Definition in Ifx_MSC.ABC.B.ABB
74  */
75 typedef enum
76 {
77  IfxMsc_AsynchronousBlock_bypassed = 0, /**< \brief Asynchronous block and the n-divider of the MSC downstream path are bypassed and are disabled */
78  IfxMsc_AsynchronousBlock_noBypassed = 1 /**< \brief Asynchronous block and the n-divider of the MSC downstream path are active */
79 } IfxMsc_AsynchronousBlock;
80 
81 /** \brief Output Control Register - Chip Selection Line Polarity\n
82  * Definition in Ifx_MSC.OCR.B.CSLP
83  */
84 typedef enum
85 {
86  IfxMsc_ChipSelectActiveState_high = 0, /**< \brief EN[3:0] and ENL,ENH,ENC polarities are identical */
87  IfxMsc_ChipSelectActiveState_low = 1 /**< \brief EN[3:0] and ENL,ENH,ENC polarities are inverted */
88 } IfxMsc_ChipSelectActiveState;
89 
90 /** \brief Asynchronous Block Configuration Register - Clock Select\n
91  * Definition in Ifx_MSC.ABC.B.CLKSEL
92  */
93 typedef enum
94 {
95  IfxMsc_ClockSelect_noClock = 0, /**< \brief no clock source for the ABRA block */
96  IfxMsc_ClockSelect_fspb = 1, /**< \brief f_SPB is the clock source for the ABRA block */
97  IfxMsc_ClockSelect_fsri = 2, /**< \brief f_SRI is the clock source for the ABRA block */
98  IfxMsc_ClockSelect_feray = 4 /**< \brief f_ERAY is the clock source for the ABRA block */
99 } IfxMsc_ClockSelect;
100 
101 /** \brief Downstream Control Enhanced Register - Command-Data-Command in Data Repetition Mode\n
102  * Definition in Ifx_MSC.DSCE.B.CDCM
103  */
104 typedef enum
105 {
106  IfxMsc_CommandDataCommandRepetitionMode_disabled = 0, /**< \brief Disables the automatic insertion of data */
107  IfxMsc_CommandDataCommandRepetitionMode_enabled = 1 /**< \brief Enables the automatic insertion of data */
108 } IfxMsc_CommandDataCommandRepetitionMode;
109 
110 /** \brief Interrupt Control Register - Command Frame Interrupt Enable\n
111  * Definition in Ifx_MSC.ICR.B.ECIE
112  */
113 typedef enum
114 {
115  IfxMsc_CommandFrameInterrupt_disabled = 0, /**< \brief Interrupt generation disabled */
116  IfxMsc_CommandFrameInterrupt_enabled = 1 /**< \brief Interrupt generation enabled */
117 } IfxMsc_CommandFrameInterrupt;
118 
119 /** \brief Interrupt Control Register - Command Frame Interrupt Node Pointer\n
120  * Definition in Ifx_MSC.ICR.B.ECIP
121  */
122 typedef enum
123 {
124  IfxMsc_CommandFrameInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
125  IfxMsc_CommandFrameInterruptNode_SR1, /**< \brief Service request output SR1 selected */
126  IfxMsc_CommandFrameInterruptNode_SR2, /**< \brief Service request output SR2 selected */
127  IfxMsc_CommandFrameInterruptNode_SR3 /**< \brief Service request output SR3 selected */
128 } IfxMsc_CommandFrameInterruptNode;
129 
130 /** \brief Number of Bits shifted at command frames\n
131  * Definition in Ifx_MSC.DSC.B.NBC
132  */
133 typedef enum
134 {
135  IfxMsc_CommandFrameLength_0 = 0, /**< \brief No bit shifted */
136  IfxMsc_CommandFrameLength_1 = 1, /**< \brief SRL[0] Shifted */
137  IfxMsc_CommandFrameLength_2 = 2, /**< \brief SRL[1:0] Shifted */
138  IfxMsc_CommandFrameLength_3, /**< \brief SRL[2:0] Shifted */
139  IfxMsc_CommandFrameLength_4, /**< \brief SRL[3:0] Shifted */
140  IfxMsc_CommandFrameLength_5, /**< \brief SRL[4:0] Shifted */
141  IfxMsc_CommandFrameLength_6, /**< \brief SRL[5:0] Shifted */
142  IfxMsc_CommandFrameLength_7, /**< \brief SRL[6:0] Shifted */
143  IfxMsc_CommandFrameLength_8, /**< \brief SRL[7:0] Shifted */
144  IfxMsc_CommandFrameLength_9, /**< \brief SRL[8:0] Shifted */
145  IfxMsc_CommandFrameLength_10, /**< \brief SRL[9:0] Shifted */
146  IfxMsc_CommandFrameLength_11, /**< \brief SRL[10:0] Shifted */
147  IfxMsc_CommandFrameLength_12, /**< \brief SRL[11:0] Shifted */
148  IfxMsc_CommandFrameLength_13, /**< \brief SRL[12:0] Shifted */
149  IfxMsc_CommandFrameLength_14, /**< \brief SRL[13:0] Shifted */
150  IfxMsc_CommandFrameLength_15, /**< \brief SRL[14:0] Shifted */
151  IfxMsc_CommandFrameLength_16, /**< \brief SRL[15:0] Shifted */
152  IfxMsc_CommandFrameLength_17 = 17, /**< \brief SRL[15:0] and SRH[0] Shifted */
153  IfxMsc_CommandFrameLength_18 = 18, /**< \brief SRL[15:0] and SRH[1:0] Shifted */
154  IfxMsc_CommandFrameLength_19, /**< \brief SRL[15:0] and SRH[2:0] Shifted */
155  IfxMsc_CommandFrameLength_20, /**< \brief SRL[15:0] and SRH[3:0] Shifted */
156  IfxMsc_CommandFrameLength_21, /**< \brief SRL[15:0] and SRH[4:0] Shifted */
157  IfxMsc_CommandFrameLength_22, /**< \brief SRL[15:0] and SRH[5:0] Shifted */
158  IfxMsc_CommandFrameLength_23, /**< \brief SRL[15:0] and SRH[6:0] Shifted */
159  IfxMsc_CommandFrameLength_24, /**< \brief SRL[15:0] and SRH[7:0] Shifted */
160  IfxMsc_CommandFrameLength_25, /**< \brief SRL[15:0] and SRH[8:0] Shifted */
161  IfxMsc_CommandFrameLength_26, /**< \brief SRL[15:0] and SRH[9:0] Shifted */
162  IfxMsc_CommandFrameLength_27, /**< \brief SRL[15:0] and SRH[10:0] Shifted */
163  IfxMsc_CommandFrameLength_28, /**< \brief SRL[15:0] and SRH[11:0] Shifted */
164  IfxMsc_CommandFrameLength_29, /**< \brief SRL[15:0] and SRH[12:0] Shifted */
165  IfxMsc_CommandFrameLength_30, /**< \brief SRL[15:0] and SRH[13:0] Shifted */
166  IfxMsc_CommandFrameLength_31, /**< \brief SRL[15:0] and SRH[14:0] Shifted */
167  IfxMsc_CommandFrameLength_32 /**< \brief SRL[15:0] and SRH[15:0] Shifted */
168 } IfxMsc_CommandFrameLength;
169 
170 /** \brief Downstream Timing Extension Register - Passive Phase Length at Control Frames Extension\n
171  * Definition in Ifx_MSC.DSTE.B.PPCE
172  */
173 typedef enum
174 {
175  IfxMsc_ControlFrameExtensionPassivePhaseLength_0 = 0, /**< \brief Length of Command frames passive phase is 2 */
176  IfxMsc_ControlFrameExtensionPassivePhaseLength_1, /**< \brief Length of Command frames passive phase is 3 */
177  IfxMsc_ControlFrameExtensionPassivePhaseLength_2, /**< \brief Length of Command frames passive phase is 4 */
178  IfxMsc_ControlFrameExtensionPassivePhaseLength_3, /**< \brief Length of Command frames passive phase is 5 */
179  IfxMsc_ControlFrameExtensionPassivePhaseLength_4, /**< \brief Length of Command frames passive phase is 6 */
180  IfxMsc_ControlFrameExtensionPassivePhaseLength_5, /**< \brief Length of Command frames passive phase is 7 */
181  IfxMsc_ControlFrameExtensionPassivePhaseLength_6, /**< \brief Length of Command frames passive phase is 8 */
182  IfxMsc_ControlFrameExtensionPassivePhaseLength_7, /**< \brief Length of Command frames passive phase is 9 */
183  IfxMsc_ControlFrameExtensionPassivePhaseLength_8, /**< \brief Length of Command frames passive phase is 10 */
184  IfxMsc_ControlFrameExtensionPassivePhaseLength_9, /**< \brief Length of Command frames passive phase is 11 */
185  IfxMsc_ControlFrameExtensionPassivePhaseLength_10, /**< \brief Length of Command frames passive phase is 12 */
186  IfxMsc_ControlFrameExtensionPassivePhaseLength_11, /**< \brief Length of Command frames passive phase is 13 */
187  IfxMsc_ControlFrameExtensionPassivePhaseLength_12, /**< \brief Length of Command frames passive phase is 14 */
188  IfxMsc_ControlFrameExtensionPassivePhaseLength_13, /**< \brief Length of Command frames passive phase is 15 */
189  IfxMsc_ControlFrameExtensionPassivePhaseLength_14, /**< \brief Length of Command frames passive phase is 16 */
190  IfxMsc_ControlFrameExtensionPassivePhaseLength_15, /**< \brief Length of Command frames passive phase is 17 */
191  IfxMsc_ControlFrameExtensionPassivePhaseLength_16, /**< \brief Length of Command frames passive phase is 18 */
192  IfxMsc_ControlFrameExtensionPassivePhaseLength_17, /**< \brief Length of Command frames passive phase is 19 */
193  IfxMsc_ControlFrameExtensionPassivePhaseLength_18, /**< \brief Length of Command frames passive phase is 20 */
194  IfxMsc_ControlFrameExtensionPassivePhaseLength_19, /**< \brief Length of Command frames passive phase is 21 */
195  IfxMsc_ControlFrameExtensionPassivePhaseLength_20, /**< \brief Length of Command frames passive phase is 22 */
196  IfxMsc_ControlFrameExtensionPassivePhaseLength_21, /**< \brief Length of Command frames passive phase is 23 */
197  IfxMsc_ControlFrameExtensionPassivePhaseLength_22, /**< \brief Length of Command frames passive phase is 24 */
198  IfxMsc_ControlFrameExtensionPassivePhaseLength_23, /**< \brief Length of Command frames passive phase is 25 */
199  IfxMsc_ControlFrameExtensionPassivePhaseLength_24, /**< \brief Length of Command frames passive phase is 26 */
200  IfxMsc_ControlFrameExtensionPassivePhaseLength_25, /**< \brief Length of Command frames passive phase is 27 */
201  IfxMsc_ControlFrameExtensionPassivePhaseLength_26, /**< \brief Length of Command frames passive phase is 28 */
202  IfxMsc_ControlFrameExtensionPassivePhaseLength_27, /**< \brief Length of Command frames passive phase is 29 */
203  IfxMsc_ControlFrameExtensionPassivePhaseLength_28, /**< \brief Length of Command frames passive phase is 30 */
204  IfxMsc_ControlFrameExtensionPassivePhaseLength_29, /**< \brief Length of Command frames passive phase is 31 */
205  IfxMsc_ControlFrameExtensionPassivePhaseLength_30, /**< \brief Length of Command frames passive phase is 32 */
206  IfxMsc_ControlFrameExtensionPassivePhaseLength_31, /**< \brief Length of Command frames passive phase is 33 */
207  IfxMsc_ControlFrameExtensionPassivePhaseLength_32, /**< \brief Length of Command frames passive phase is 34 */
208  IfxMsc_ControlFrameExtensionPassivePhaseLength_33, /**< \brief Length of Command frames passive phase is 35 */
209  IfxMsc_ControlFrameExtensionPassivePhaseLength_34, /**< \brief Length of Command frames passive phase is 36 */
210  IfxMsc_ControlFrameExtensionPassivePhaseLength_35, /**< \brief Length of Command frames passive phase is 37 */
211  IfxMsc_ControlFrameExtensionPassivePhaseLength_36, /**< \brief Length of Command frames passive phase is 38 */
212  IfxMsc_ControlFrameExtensionPassivePhaseLength_37, /**< \brief Length of Command frames passive phase is 39 */
213  IfxMsc_ControlFrameExtensionPassivePhaseLength_38, /**< \brief Length of Command frames passive phase is 40 */
214  IfxMsc_ControlFrameExtensionPassivePhaseLength_39, /**< \brief Length of Command frames passive phase is 41 */
215  IfxMsc_ControlFrameExtensionPassivePhaseLength_40, /**< \brief Length of Command frames passive phase is 42 */
216  IfxMsc_ControlFrameExtensionPassivePhaseLength_41, /**< \brief Length of Command frames passive phase is 43 */
217  IfxMsc_ControlFrameExtensionPassivePhaseLength_42, /**< \brief Length of Command frames passive phase is 44 */
218  IfxMsc_ControlFrameExtensionPassivePhaseLength_43, /**< \brief Length of Command frames passive phase is 45 */
219  IfxMsc_ControlFrameExtensionPassivePhaseLength_44, /**< \brief Length of Command frames passive phase is 46 */
220  IfxMsc_ControlFrameExtensionPassivePhaseLength_45, /**< \brief Length of Command frames passive phase is 47 */
221  IfxMsc_ControlFrameExtensionPassivePhaseLength_46, /**< \brief Length of Command frames passive phase is 48 */
222  IfxMsc_ControlFrameExtensionPassivePhaseLength_47, /**< \brief Length of Command frames passive phase is 49 */
223  IfxMsc_ControlFrameExtensionPassivePhaseLength_48, /**< \brief Length of Command frames passive phase is 50 */
224  IfxMsc_ControlFrameExtensionPassivePhaseLength_49, /**< \brief Length of Command frames passive phase is 51 */
225  IfxMsc_ControlFrameExtensionPassivePhaseLength_50, /**< \brief Length of Command frames passive phase is 52 */
226  IfxMsc_ControlFrameExtensionPassivePhaseLength_51, /**< \brief Length of Command frames passive phase is 53 */
227  IfxMsc_ControlFrameExtensionPassivePhaseLength_52, /**< \brief Length of Command frames passive phase is 54 */
228  IfxMsc_ControlFrameExtensionPassivePhaseLength_53, /**< \brief Length of Command frames passive phase is 55 */
229  IfxMsc_ControlFrameExtensionPassivePhaseLength_54, /**< \brief Length of Command frames passive phase is 56 */
230  IfxMsc_ControlFrameExtensionPassivePhaseLength_55, /**< \brief Length of Command frames passive phase is 57 */
231  IfxMsc_ControlFrameExtensionPassivePhaseLength_56, /**< \brief Length of Command frames passive phase is 58 */
232  IfxMsc_ControlFrameExtensionPassivePhaseLength_57, /**< \brief Length of Command frames passive phase is 59 */
233  IfxMsc_ControlFrameExtensionPassivePhaseLength_58, /**< \brief Length of Command frames passive phase is 60 */
234  IfxMsc_ControlFrameExtensionPassivePhaseLength_59, /**< \brief Length of Command frames passive phase is 61 */
235  IfxMsc_ControlFrameExtensionPassivePhaseLength_60, /**< \brief Length of Command frames passive phase is 62 */
236  IfxMsc_ControlFrameExtensionPassivePhaseLength_61, /**< \brief Length of Command frames passive phase is 63 */
237  IfxMsc_ControlFrameExtensionPassivePhaseLength_62, /**< \brief Length of Command frames passive phase is 64 */
238  IfxMsc_ControlFrameExtensionPassivePhaseLength_63 /**< \brief Length of Command frames passive phase is 65 */
239 } IfxMsc_ControlFrameExtensionPassivePhaseLength;
240 
241 /** \brief Downstream Timing Extension Register - Passive Phase Length at Data Frames Extension\n
242  * Definition in Ifx_MSC.DSTE.B.PPDE
243  */
244 typedef enum
245 {
246  IfxMsc_DataFrameExtensionPassivePhaseLength_0 = 0, /**< \brief 0 Additional MSB bits extension of the PPD bit field */
247  IfxMsc_DataFrameExtensionPassivePhaseLength_1, /**< \brief 1 Additional MSB bits extension of the PPD bit field */
248  IfxMsc_DataFrameExtensionPassivePhaseLength_2, /**< \brief 2 Additional MSB bits extension of the PPD bit field */
249  IfxMsc_DataFrameExtensionPassivePhaseLength_3 /**< \brief 3 Additional MSB bits extension of the PPD bit field */
250 } IfxMsc_DataFrameExtensionPassivePhaseLength;
251 
252 /** \brief Interrupt Control Register - Data Frame Interrupt Enable\n
253  * Definition in Ifx_MSC.ICR.B.EDIE
254  */
255 typedef enum
256 {
257  IfxMsc_DataFrameInterrupt_disabled = 0, /**< \brief Interrupt generation Disable */
258  IfxMsc_DataFrameInterrupt_atLastDataBit = 1, /**< \brief An interrupt is generated when the last data bit has been shifted out */
259  IfxMsc_DataFrameInterrupt_atFirstDataBit = 2 /**< \brief An interrupt is generated when the First data bit has been shifted out */
260 } IfxMsc_DataFrameInterrupt;
261 
262 /** \brief Interrupt Control Register - Data Frame Interrupt Node Pointer\n
263  * Definition in Ifx_MSC.ICR.B.EDIP
264  */
265 typedef enum
266 {
267  IfxMsc_DataFrameInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
268  IfxMsc_DataFrameInterruptNode_SR1, /**< \brief Service request output SR1 selected */
269  IfxMsc_DataFrameInterruptNode_SR2, /**< \brief Service request output SR2 selected */
270  IfxMsc_DataFrameInterruptNode_SR3 /**< \brief Service request output SR3 selected */
271 } IfxMsc_DataFrameInterruptNode;
272 
273 /** \brief Number of SRx[] (x->SRL/SRH) Bits Shifted at Data Frames\n
274  * Definition in Ifx_MSC.DSC.B.NDBH and Ifx_MSC.DSC.B.NDBL
275  */
276 typedef enum
277 {
278  IfxMsc_DataFrameLength_0 = 0, /**< \brief No SRx bit shifted */
279  IfxMsc_DataFrameLength_1 = 1, /**< \brief SRx[0] Shifted */
280  IfxMsc_DataFrameLength_2 = 2, /**< \brief SRx[1:0] Shifted */
281  IfxMsc_DataFrameLength_3, /**< \brief SRx[2:0] Shifted */
282  IfxMsc_DataFrameLength_4, /**< \brief SRx[3:0] Shifted */
283  IfxMsc_DataFrameLength_5, /**< \brief SRx[4:0] Shifted */
284  IfxMsc_DataFrameLength_6, /**< \brief SRx[5:0] Shifted */
285  IfxMsc_DataFrameLength_7, /**< \brief SRx[6:0] Shifted */
286  IfxMsc_DataFrameLength_8, /**< \brief SRx[7:0] Shifted */
287  IfxMsc_DataFrameLength_9, /**< \brief SRx[8:0] Shifted */
288  IfxMsc_DataFrameLength_10, /**< \brief SRx[9:0] Shifted */
289  IfxMsc_DataFrameLength_11, /**< \brief SRx[10:0] Shifted */
290  IfxMsc_DataFrameLength_12, /**< \brief SRx[11:0] Shifted */
291  IfxMsc_DataFrameLength_13, /**< \brief SRx[12:0] Shifted */
292  IfxMsc_DataFrameLength_14, /**< \brief SRx[13:0] Shifted */
293  IfxMsc_DataFrameLength_15, /**< \brief SRx[14:0] Shifted */
294  IfxMsc_DataFrameLength_16 /**< \brief SRx[15:0] Shifted */
295 } IfxMsc_DataFrameLength;
296 
297 /** \brief Passive Phase Length at Data Frames\n
298  * Definition in Ifx_MSC.DSC.B.PPD
299  */
300 typedef enum
301 {
302  IfxMsc_DataFramePassivePhaseLength_2 = 2, /**< \brief Passive phase length is 2 tFCL */
303  IfxMsc_DataFramePassivePhaseLength_3, /**< \brief Passive phase length is 3 tFCL */
304  IfxMsc_DataFramePassivePhaseLength_4, /**< \brief Passive phase length is 4 tFCL */
305  IfxMsc_DataFramePassivePhaseLength_5, /**< \brief Passive phase length is 5 tFCL */
306  IfxMsc_DataFramePassivePhaseLength_6, /**< \brief Passive phase length is 6 tFCL */
307  IfxMsc_DataFramePassivePhaseLength_7, /**< \brief Passive phase length is 7 tFCL */
308  IfxMsc_DataFramePassivePhaseLength_8, /**< \brief Passive phase length is 8 tFCL */
309  IfxMsc_DataFramePassivePhaseLength_9, /**< \brief Passive phase length is 9 tFCL */
310  IfxMsc_DataFramePassivePhaseLength_10, /**< \brief Passive phase length is 10 tFCL */
311  IfxMsc_DataFramePassivePhaseLength_11, /**< \brief Passive phase length is 11 tFCL */
312  IfxMsc_DataFramePassivePhaseLength_12, /**< \brief Passive phase length is 12 tFCL */
313  IfxMsc_DataFramePassivePhaseLength_13, /**< \brief Passive phase length is 13 tFCL */
314  IfxMsc_DataFramePassivePhaseLength_14, /**< \brief Passive phase length is 14 tFCL */
315  IfxMsc_DataFramePassivePhaseLength_15, /**< \brief Passive phase length is 15 tFCL */
316  IfxMsc_DataFramePassivePhaseLength_16, /**< \brief Passive phase length is 16 tFCL */
317  IfxMsc_DataFramePassivePhaseLength_17, /**< \brief Passive phase length is 17 tFCL */
318  IfxMsc_DataFramePassivePhaseLength_18, /**< \brief Passive phase length is 18 tFCL */
319  IfxMsc_DataFramePassivePhaseLength_19, /**< \brief Passive phase length is 19 tFCL */
320  IfxMsc_DataFramePassivePhaseLength_20, /**< \brief Passive phase length is 20 tFCL */
321  IfxMsc_DataFramePassivePhaseLength_21, /**< \brief Passive phase length is 21 tFCL */
322  IfxMsc_DataFramePassivePhaseLength_22, /**< \brief Passive phase length is 22 tFCL */
323  IfxMsc_DataFramePassivePhaseLength_23, /**< \brief Passive phase length is 23 tFCL */
324  IfxMsc_DataFramePassivePhaseLength_24, /**< \brief Passive phase length is 24 tFCL */
325  IfxMsc_DataFramePassivePhaseLength_25, /**< \brief Passive phase length is 25 tFCL */
326  IfxMsc_DataFramePassivePhaseLength_26, /**< \brief Passive phase length is 26 tFCL */
327  IfxMsc_DataFramePassivePhaseLength_27, /**< \brief Passive phase length is 27 tFCL */
328  IfxMsc_DataFramePassivePhaseLength_28, /**< \brief Passive phase length is 28 tFCL */
329  IfxMsc_DataFramePassivePhaseLength_29, /**< \brief Passive phase length is 29 tFCL */
330  IfxMsc_DataFramePassivePhaseLength_30, /**< \brief Passive phase length is 30 tFCL */
331  IfxMsc_DataFramePassivePhaseLength_31, /**< \brief Passive phase length is 31 tFCL */
332  IfxMsc_DataFramePassivePhaseLength_32 /**< \brief Passive phase length is 32 tFCL */
333 } IfxMsc_DataFramePassivePhaseLength;
334 
335 /** \brief Divider mode
336  */
337 typedef enum
338 {
339  IfxMsc_DividerMode_normal = 1, /**< \brief divider mode is normal */
340  IfxMsc_DividerMode_fractional = 2 /**< \brief divider mode is fractional */
341 } IfxMsc_DividerMode;
342 
343 /** \brief Emergency Stop Register - Emergency stop feature Enable or Disable - SRL and SRH\n
344  * Definition in Ifx_MSC.ESR
345  */
346 typedef enum
347 {
348  IfxMsc_EmergencyStop_disabled = 0, /**< \brief Emergency stop feature for SRx bit is Disabled */
349  IfxMsc_EmergencyStop_enabled = 1 /**< \brief Emergency stop feature for SRx bit is Enabled */
350 } IfxMsc_EmergencyStop;
351 
352 /** \brief Downstream Control Enhanced Register - Extension Enable\n
353  * Definition in Ifx_MSC.DSCE.B.NDBLE
354  */
355 typedef enum
356 {
357  IfxMsc_Extension_disabled = 0, /**< \brief Disables the extension bit fields */
358  IfxMsc_Extension_enabled = 1 /**< \brief Enables the extension bit fields */
359 } IfxMsc_Extension;
360 
361 /** \brief Downstream Control Enhanced Register - Injection Position of the Pin 0 and 1 Signal\n
362  * Definition in Ifx_MSC.DSCE.B.INJPOSP0 and Ifx_MSC.DSCE.B.INJPOSP1
363  */
364 typedef enum
365 {
366  IfxMsc_ExternalBitInjectionPosition_0 = 0, /**< \brief Injected external bit is at Position 0 of the data frame */
367  IfxMsc_ExternalBitInjectionPosition_1, /**< \brief Injected external bit is at Position 1 of the data frame */
368  IfxMsc_ExternalBitInjectionPosition_2, /**< \brief Injected external bit is at Position 2 of the data frame */
369  IfxMsc_ExternalBitInjectionPosition_3, /**< \brief Injected external bit is at Position 3 of the data frame */
370  IfxMsc_ExternalBitInjectionPosition_4, /**< \brief Injected external bit is at Position 4 of the data frame */
371  IfxMsc_ExternalBitInjectionPosition_5, /**< \brief Injected external bit is at Position 5 of the data frame */
372  IfxMsc_ExternalBitInjectionPosition_6, /**< \brief Injected external bit is at Position 6 of the data frame */
373  IfxMsc_ExternalBitInjectionPosition_7, /**< \brief Injected external bit is at Position 7 of the data frame */
374  IfxMsc_ExternalBitInjectionPosition_8, /**< \brief Injected external bit is at Position 8 of the data frame */
375  IfxMsc_ExternalBitInjectionPosition_9, /**< \brief Injected external bit is at Position 9 of the data frame */
376  IfxMsc_ExternalBitInjectionPosition_10, /**< \brief Injected external bit is at Position 10 of the data frame */
377  IfxMsc_ExternalBitInjectionPosition_11, /**< \brief Injected external bit is at Position 11 of the data frame */
378  IfxMsc_ExternalBitInjectionPosition_12, /**< \brief Injected external bit is at Position 12 of the data frame */
379  IfxMsc_ExternalBitInjectionPosition_13, /**< \brief Injected external bit is at Position 13 of the data frame */
380  IfxMsc_ExternalBitInjectionPosition_14, /**< \brief Injected external bit is at Position 14 of the data frame */
381  IfxMsc_ExternalBitInjectionPosition_15, /**< \brief Injected external bit is at Position 15 of the data frame */
382  IfxMsc_ExternalBitInjectionPosition_16, /**< \brief Injected external bit is at Position 16 of the data frame */
383  IfxMsc_ExternalBitInjectionPosition_17, /**< \brief Injected external bit is at Position 17 of the data frame */
384  IfxMsc_ExternalBitInjectionPosition_18, /**< \brief Injected external bit is at Position 18 of the data frame */
385  IfxMsc_ExternalBitInjectionPosition_19, /**< \brief Injected external bit is at Position 19 of the data frame */
386  IfxMsc_ExternalBitInjectionPosition_20, /**< \brief Injected external bit is at Position 20 of the data frame */
387  IfxMsc_ExternalBitInjectionPosition_21, /**< \brief Injected external bit is at Position 21 of the data frame */
388  IfxMsc_ExternalBitInjectionPosition_22, /**< \brief Injected external bit is at Position 22 of the data frame */
389  IfxMsc_ExternalBitInjectionPosition_23, /**< \brief Injected external bit is at Position 23 of the data frame */
390  IfxMsc_ExternalBitInjectionPosition_24, /**< \brief Injected external bit is at Position 24 of the data frame */
391  IfxMsc_ExternalBitInjectionPosition_25, /**< \brief Injected external bit is at Position 25 of the data frame */
392  IfxMsc_ExternalBitInjectionPosition_26, /**< \brief Injected external bit is at Position 26 of the data frame */
393  IfxMsc_ExternalBitInjectionPosition_27, /**< \brief Injected external bit is at Position 27 of the data frame */
394  IfxMsc_ExternalBitInjectionPosition_28, /**< \brief Injected external bit is at Position 28 of the data frame */
395  IfxMsc_ExternalBitInjectionPosition_29, /**< \brief Injected external bit is at Position 29 of the data frame */
396  IfxMsc_ExternalBitInjectionPosition_30, /**< \brief Injected external bit is at Position 30 of the data frame */
397  IfxMsc_ExternalBitInjectionPosition_31, /**< \brief Injected external bit is at Position 31 of the data frame */
398  IfxMsc_ExternalBitInjectionPosition_32, /**< \brief Injected external bit is at Position 32 of the data frame */
399  IfxMsc_ExternalBitInjectionPosition_33, /**< \brief Injected external bit is at Position 33 of the data frame */
400  IfxMsc_ExternalBitInjectionPosition_34, /**< \brief Injected external bit is at Position 34 of the data frame */
401  IfxMsc_ExternalBitInjectionPosition_35, /**< \brief Injected external bit is at Position 35 of the data frame */
402  IfxMsc_ExternalBitInjectionPosition_36, /**< \brief Injected external bit is at Position 36 of the data frame */
403  IfxMsc_ExternalBitInjectionPosition_37, /**< \brief Injected external bit is at Position 37 of the data frame */
404  IfxMsc_ExternalBitInjectionPosition_38, /**< \brief Injected external bit is at Position 38 of the data frame */
405  IfxMsc_ExternalBitInjectionPosition_39, /**< \brief Injected external bit is at Position 39 of the data frame */
406  IfxMsc_ExternalBitInjectionPosition_40, /**< \brief Injected external bit is at Position 40 of the data frame */
407  IfxMsc_ExternalBitInjectionPosition_41, /**< \brief Injected external bit is at Position 41 of the data frame */
408  IfxMsc_ExternalBitInjectionPosition_42, /**< \brief Injected external bit is at Position 42 of the data frame */
409  IfxMsc_ExternalBitInjectionPosition_43, /**< \brief Injected external bit is at Position 43 of the data frame */
410  IfxMsc_ExternalBitInjectionPosition_44, /**< \brief Injected external bit is at Position 44 of the data frame */
411  IfxMsc_ExternalBitInjectionPosition_45, /**< \brief Injected external bit is at Position 45 of the data frame */
412  IfxMsc_ExternalBitInjectionPosition_46, /**< \brief Injected external bit is at Position 46 of the data frame */
413  IfxMsc_ExternalBitInjectionPosition_47, /**< \brief Injected external bit is at Position 47 of the data frame */
414  IfxMsc_ExternalBitInjectionPosition_48, /**< \brief Injected external bit is at Position 48 of the data frame */
415  IfxMsc_ExternalBitInjectionPosition_49, /**< \brief Injected external bit is at Position 49 of the data frame */
416  IfxMsc_ExternalBitInjectionPosition_50, /**< \brief Injected external bit is at Position 50 of the data frame */
417  IfxMsc_ExternalBitInjectionPosition_51, /**< \brief Injected external bit is at Position 51 of the data frame */
418  IfxMsc_ExternalBitInjectionPosition_52, /**< \brief Injected external bit is at Position 52 of the data frame */
419  IfxMsc_ExternalBitInjectionPosition_53, /**< \brief Injected external bit is at Position 53 of the data frame */
420  IfxMsc_ExternalBitInjectionPosition_54, /**< \brief Injected external bit is at Position 54 of the data frame */
421  IfxMsc_ExternalBitInjectionPosition_55, /**< \brief Injected external bit is at Position 55 of the data frame */
422  IfxMsc_ExternalBitInjectionPosition_56, /**< \brief Injected external bit is at Position 56 of the data frame */
423  IfxMsc_ExternalBitInjectionPosition_57, /**< \brief Injected external bit is at Position 57 of the data frame */
424  IfxMsc_ExternalBitInjectionPosition_58, /**< \brief Injected external bit is at Position 58 of the data frame */
425  IfxMsc_ExternalBitInjectionPosition_59, /**< \brief Injected external bit is at Position 59 of the data frame */
426  IfxMsc_ExternalBitInjectionPosition_60, /**< \brief Injected external bit is at Position 60 of the data frame */
427  IfxMsc_ExternalBitInjectionPosition_61, /**< \brief Injected external bit is at Position 61 of the data frame */
428  IfxMsc_ExternalBitInjectionPosition_62, /**< \brief Injected external bit is at Position 62 of the data frame */
429  IfxMsc_ExternalBitInjectionPosition_63 /**< \brief Injected external bit is at Position 63 of the data frame */
430 } IfxMsc_ExternalBitInjectionPosition;
431 
432 /** \brief Downstream Control Enhanced Register - Injection Enable of the Pin 0 and 1 Signal\n
433  * Definition in Ifx_MSC.DSCE.B.INJENP0 and Ifx_MSC.DSCE.B.INJENP1
434  */
435 typedef enum
436 {
437  IfxMsc_ExternalSignalInjection_disabled = 0, /**< \brief Disables the external signal injection in a data frame */
438  IfxMsc_ExternalSignalInjection_enabled = 1 /**< \brief Enables the external signal injection in a data frame */
439 } IfxMsc_ExternalSignalInjection;
440 
441 /** \brief Output Control Register - Clock Control\n
442  * Definition in Ifx_MSC.OCR.B.CLKCTRL
443  */
444 typedef enum
445 {
446  IfxMsc_FclClockControlEnabled_activePhaseOnly = 0, /**< \brief FCL is active during active phases of data or command frames */
447  IfxMsc_FclClockControlEnabled_always = 1 /**< \brief FCL is always active */
448 } IfxMsc_FclClockControlEnabled;
449 
450 /** \brief Output Control Register - FCLP Line Polarity\n
451  * Definition in Ifx_MSC.OCR.B.CLP
452  */
453 typedef enum
454 {
455  IfxMsc_FclLinePolarity_nonInverted = 0, /**< \brief FCLP and FCL signal polarity is identical */
456  IfxMsc_FclLinePolarity_inverted = 1 /**< \brief FCLP signal has inverted FCL signal polarity */
457 } IfxMsc_FclLinePolarity;
458 
459 /** \brief Enable hardware clock control
460  */
461 typedef enum
462 {
463  IfxMsc_HardwareClock_disabled = 0, /**< \brief Hardware clock disable */
464  IfxMsc_HardwareClock_enabled = 1 /**< \brief Hardware clock enable */
465 } IfxMsc_HardwareClock;
466 
467 /** \brief OCDS Control and Status - OCDS Suspend Control
468  * Definition in Ifx_MSC.OCS.B.SUS
469  */
470 typedef enum
471 {
472  IfxMsc_ModuleSuspendRequestBit_noSuspend = 0, /**< \brief OCDS is not suspended */
473  IfxMsc_ModuleSuspendRequestBit_hardSuspend = 1, /**< \brief OCDS is Hard suspended. Clock is switched off immediately */
474  IfxMsc_ModuleSuspendRequestBit_softSuspend = 2 /**< \brief OCDS is Soft suspended */
475 } IfxMsc_ModuleSuspendRequestBit;
476 
477 /** \brief Downstream Control Enhanced Register - Number of SRL/SRH Bits Shifted at Data Frames Extension (NDBL/NDBH)\n
478  * Definition in Ifx_MSC.DSCE.B.NDBLE and Ifx_MSC.DSCE.B.NDBHE
479  */
480 typedef enum
481 {
482  IfxMsc_MsbBitDataExtension_notPresent = 0, /**< \brief Additional MSB bit is not present in the extension of the NDBL/NDBH bit field */
483  IfxMsc_MsbBitDataExtension_present = 1 /**< \brief Additional MSB bit is present in the extension of the NDBL/NDBH bit field */
484 } IfxMsc_MsbBitDataExtension;
485 
486 /** \brief Asynchronous Block Configuration Register - N Divider ABRA\n
487  * Definition in Ifx_MSC.ABC.B.NDA
488  */
489 typedef enum
490 {
491  IfxMsc_NDividerAbra_1 = 0, /**< \brief Division ratio is 1 */
492  IfxMsc_NDividerAbra_2, /**< \brief Division ratio is 2 */
493  IfxMsc_NDividerAbra_3, /**< \brief Division ratio is 3 */
494  IfxMsc_NDividerAbra_4, /**< \brief Division ratio is 4 */
495  IfxMsc_NDividerAbra_5, /**< \brief Division ratio is 5 */
496  IfxMsc_NDividerAbra_6, /**< \brief Division ratio is 6 */
497  IfxMsc_NDividerAbra_7, /**< \brief Division ratio is 7 */
498  IfxMsc_NDividerAbra_8 /**< \brief Division ratio is 8 */
499 } IfxMsc_NDividerAbra;
500 
501 /** \brief Downstream Timing Extension Register - N Divider Downstream\n
502  * Definition in Ifx_MSC.DSTE.B.NDD
503  */
504 typedef enum
505 {
506  IfxMsc_NDividerDownstream_1 = 0, /**< \brief division ratio is 1 */
507  IfxMsc_NDividerDownstream_2, /**< \brief division ratio is 2 */
508  IfxMsc_NDividerDownstream_3, /**< \brief division ratio is 3 */
509  IfxMsc_NDividerDownstream_4, /**< \brief division ratio is 4 */
510  IfxMsc_NDividerDownstream_5, /**< \brief division ratio is 5 */
511  IfxMsc_NDividerDownstream_6, /**< \brief division ratio is 6 */
512  IfxMsc_NDividerDownstream_7, /**< \brief division ratio is 7 */
513  IfxMsc_NDividerDownstream_8, /**< \brief division ratio is 8 */
514  IfxMsc_NDividerDownstream_9, /**< \brief division ratio is 9 */
515  IfxMsc_NDividerDownstream_10, /**< \brief division ratio is 10 */
516  IfxMsc_NDividerDownstream_11, /**< \brief division ratio is 11 */
517  IfxMsc_NDividerDownstream_12, /**< \brief division ratio is 12 */
518  IfxMsc_NDividerDownstream_13, /**< \brief division ratio is 13 */
519  IfxMsc_NDividerDownstream_14, /**< \brief division ratio is 14 */
520  IfxMsc_NDividerDownstream_15, /**< \brief division ratio is 15 */
521  IfxMsc_NDividerDownstream_16 /**< \brief division ratio is 16 */
522 } IfxMsc_NDividerDownstream;
523 
524 /** \brief Asynchronous Block Configuration Register - Overflow Interrupt Enable\n
525  * Definition in Ifx_MSC.ABC.B.OIE
526  */
527 typedef enum
528 {
529  IfxMsc_OverflowInterrupt_disabled = 0, /**< \brief Disables the path of the overflow interrupt towards the interrupt node */
530  IfxMsc_OverflowInterrupt_enabled = 1 /**< \brief Enables the path of the overflow interrupt towards the interrupt node */
531 } IfxMsc_OverflowInterrupt;
532 
533 /** \brief Asynchronous Block Configuration Register - Overflow Interrupt Node Pointer\n
534  * Definition in Ifx_MSC.ABC.B.OIP
535  */
536 typedef enum
537 {
538  IfxMsc_OverflowInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
539  IfxMsc_OverflowInterruptNode_SR1, /**< \brief Service request output SR1 selected */
540  IfxMsc_OverflowInterruptNode_SR2, /**< \brief Service request output SR2 selected */
541  IfxMsc_OverflowInterruptNode_SR3, /**< \brief Service request output SR3 selected */
542  IfxMsc_OverflowInterruptNode_SR4 /**< \brief Service request output SR4 selected */
543 } IfxMsc_OverflowInterruptNode;
544 
545 /** \brief Parity Mode\n
546  * Definition in Ifx_MSC.USR.B.PCT
547  */
548 typedef enum
549 {
550  IfxMsc_Parity_even = 0, /**< \brief Even Parity */
551  IfxMsc_Parity_odd = 1 /**< \brief Odd Parity */
552 } IfxMsc_Parity;
553 
554 /** \brief Downstream Status Register - Number Of Passive Time Frames\n
555  * Definition in Ifx_MSC.DSS.B.NPTF
556  */
557 typedef enum
558 {
559  IfxMsc_PassiveTimeFrameCount_0 = 0, /**< \brief No Passive time frames inserted */
560  IfxMsc_PassiveTimeFrameCount_1 = 1, /**< \brief 1 Passive time frames inserted */
561  IfxMsc_PassiveTimeFrameCount_2, /**< \brief 2 Passive time frames inserted */
562  IfxMsc_PassiveTimeFrameCount_3, /**< \brief 3 Passive time frames inserted */
563  IfxMsc_PassiveTimeFrameCount_4, /**< \brief 4 Passive time frames inserted */
564  IfxMsc_PassiveTimeFrameCount_5, /**< \brief 5 Passive time frames inserted */
565  IfxMsc_PassiveTimeFrameCount_6, /**< \brief 6 Passive time frames inserted */
566  IfxMsc_PassiveTimeFrameCount_7, /**< \brief 7 Passive time frames inserted */
567  IfxMsc_PassiveTimeFrameCount_8, /**< \brief 8 Passive time frames inserted */
568  IfxMsc_PassiveTimeFrameCount_9, /**< \brief 9 Passive time frames inserted */
569  IfxMsc_PassiveTimeFrameCount_10, /**< \brief 10 Passive time frames inserted */
570  IfxMsc_PassiveTimeFrameCount_11, /**< \brief 11 Passive time frames inserted */
571  IfxMsc_PassiveTimeFrameCount_12, /**< \brief 12 Passive time frames inserted */
572  IfxMsc_PassiveTimeFrameCount_13, /**< \brief 13 Passive time frames inserted */
573  IfxMsc_PassiveTimeFrameCount_14, /**< \brief 14 Passive time frames inserted */
574  IfxMsc_PassiveTimeFrameCount_15 /**< \brief 15 Passive time frames inserted */
575 } IfxMsc_PassiveTimeFrameCount;
576 
577 /** \brief Interrupt Control Register - Receive Data Interrupt Enable\n
578  * Definition in Ifx_MSC.ICR.B.RDIE
579  */
580 typedef enum
581 {
582  IfxMsc_ReceiveDataInterrupt_disabled = 0, /**< \brief Interrupt generation disabled */
583  IfxMsc_ReceiveDataInterrupt_onDataReceive = 1, /**< \brief An interrupt is generated when data is received and written into the upstream data registers */
584  IfxMsc_ReceiveDataInterrupt_onRdieSet = 2, /**< \brief An interrupt is generated as with RDIE = 01B but only if the received data is not equal to 00H */
585  IfxMsc_ReceiveDataInterrupt_onDataReceiveInUd3 = 3 /**< \brief An interrupt is generated as with RDIE = 01B but only if the received data is not equal to 00H */
586 } IfxMsc_ReceiveDataInterrupt;
587 
588 /** \brief Interrupt Control Register - Receive Data Interrupt Pointer\n
589  * Definition in Ifx_MSC.ICR.B.RDIP
590  */
591 typedef enum
592 {
593  IfxMsc_ReceiveDataInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
594  IfxMsc_ReceiveDataInterruptNode_SR1, /**< \brief Service request output SR1 selected */
595  IfxMsc_ReceiveDataInterruptNode_SR2, /**< \brief Service request output SR2 selected */
596  IfxMsc_ReceiveDataInterruptNode_SR3 /**< \brief Service request output SR3 selected */
597 } IfxMsc_ReceiveDataInterruptNode;
598 
599 /** \brief Output Control Register - SDI Line Polarity\n
600  * Definition in Ifx_MSC.OCR.B.ILP
601  */
602 typedef enum
603 {
604  IfxMsc_SdiLinePolarity_likeSi = 0, /**< \brief SDI and SI signal polarities are identical */
605  IfxMsc_SdiLinePolarity_invertedSi = 1 /**< \brief SDI and SI signal polarities are inverted */
606 } IfxMsc_SdiLinePolarity;
607 
608 /** \brief Output Control Register - Serial Data Input Selection\n
609  * Definition in Ifx_MSC.OCR.B.SDISEL
610  */
611 typedef enum
612 {
613  IfxMsc_SerialDataInput_0 = 0, /**< \brief SDI0 is selected for the SDI of the upstream channel */
614  IfxMsc_SerialDataInput_1, /**< \brief SDI1 is selected for the SDI of the upstream channel */
615  IfxMsc_SerialDataInput_2, /**< \brief SDI2 is selected for the SDI of the upstream channel */
616  IfxMsc_SerialDataInput_3, /**< \brief SDI3 is selected for the SDI of the upstream channel */
617  IfxMsc_SerialDataInput_4, /**< \brief SDI4 is selected for the SDI of the upstream channel */
618  IfxMsc_SerialDataInput_5, /**< \brief SDI5 is selected for the SDI of the upstream channel */
619  IfxMsc_SerialDataInput_6, /**< \brief SDI6 is selected for the SDI of the upstream channel */
620  IfxMsc_SerialDataInput_7 /**< \brief SDI7 is selected for the SDI of the upstream channel */
621 } IfxMsc_SerialDataInput;
622 
623 /** \brief Service Request Delay\n
624  * Definition in Ifx_MSC.USR.B.SRDC
625  */
626 typedef enum
627 {
628  IfxMsc_ServiceRequestDelay_noDelay = 0, /**< \brief No Delay */
629  IfxMsc_ServiceRequestDelay_1bit = 1 /**< \brief Delay of 1 bit time */
630 } IfxMsc_ServiceRequestDelay;
631 
632 /** \brief Asynchronous Block Configuration Register - Duration of the Low/High Phase of the Shift Clock\n
633  * Definition in Ifx_MSC.ABC.B.LOW and Ifx_MSC.ABC.B.HIGH
634  */
635 typedef enum
636 {
637  IfxMsc_ShiftClockPhaseDuration_1 = 0, /**< \brief Duration in periods of f_A is 1 */
638  IfxMsc_ShiftClockPhaseDuration_2, /**< \brief Duration in periods of f_A is 2 */
639  IfxMsc_ShiftClockPhaseDuration_3, /**< \brief Duration in periods of f_A is 3 */
640  IfxMsc_ShiftClockPhaseDuration_4, /**< \brief Duration in periods of f_A is 4 */
641  IfxMsc_ShiftClockPhaseDuration_5, /**< \brief Duration in periods of f_A is 5 */
642  IfxMsc_ShiftClockPhaseDuration_6, /**< \brief Duration in periods of f_A is 6 */
643  IfxMsc_ShiftClockPhaseDuration_7, /**< \brief Duration in periods of f_A is 7 */
644  IfxMsc_ShiftClockPhaseDuration_8, /**< \brief Duration in periods of f_A is 8 */
645  IfxMsc_ShiftClockPhaseDuration_9, /**< \brief Duration in periods of f_A is 9 */
646  IfxMsc_ShiftClockPhaseDuration_10, /**< \brief Duration in periods of f_A is 10 */
647  IfxMsc_ShiftClockPhaseDuration_11, /**< \brief Duration in periods of f_A is 11 */
648  IfxMsc_ShiftClockPhaseDuration_12, /**< \brief Duration in periods of f_A is 12 */
649  IfxMsc_ShiftClockPhaseDuration_13, /**< \brief Duration in periods of f_A is 13 */
650  IfxMsc_ShiftClockPhaseDuration_14, /**< \brief Duration in periods of f_A is 14 */
651  IfxMsc_ShiftClockPhaseDuration_15, /**< \brief Duration in periods of f_A is 15 */
652  IfxMsc_ShiftClockPhaseDuration_16 /**< \brief Duration in periods of f_A is 16 */
653 } IfxMsc_ShiftClockPhaseDuration;
654 
655 /** \brief Enable/disable the sensitivity of the module to sleep signal\n
656  * Definition in Ifx_MSC.CLC.B.EDIS
657  */
658 typedef enum
659 {
660  IfxMsc_SleepMode_enable = 0, /**< \brief enables sleep mode */
661  IfxMsc_SleepMode_disable = 1 /**< \brief disables sleep mode */
662 } IfxMsc_SleepMode;
663 
664 /** \brief Output Control Register - SOP Line Polarity\n
665  * Definition in Ifx_MSC.OCR.B.SLP
666  */
667 typedef enum
668 {
669  IfxMsc_SoLinePolarity_nonInverted = 0, /**< \brief SOP and SO polarity is identical */
670  IfxMsc_SoLinePolarity_inverted = 1 /**< \brief SOP and SO polarity is inverted */
671 } IfxMsc_SoLinePolarity;
672 
673 /** \brief Downstream Select Data Source Low Register - Select Source for - SRL and SRHNumber Of Passive Time Frames\n
674  * Definition in Ifx_MSC.DSDSL and Ifx_MSC.DSDSH
675  */
676 typedef enum
677 {
678  IfxMsc_Source_downstreamDataRegister = 0, /**< \brief SRx[16] is taken from data Register DD.DDL[xx] */
679  IfxMsc_Source_alternateInputLine = 2, /**< \brief SRx[16] is taken from ALTINL input line */
680  IfxMsc_Source_alternateInputLineInverted = 3 /**< \brief SRx[16] is taken from ALTINL input line in inverted state */
681 } IfxMsc_Source;
682 
683 /** \brief Msc Targets - use as chip enable selection for ENH, ENL and ENC
684  */
685 typedef enum
686 {
687  IfxMsc_Target_en0 = 0, /**< \brief Target EN0 */
688  IfxMsc_Target_en1, /**< \brief Target EN1 */
689  IfxMsc_Target_en2, /**< \brief Target EN2 */
690  IfxMsc_Target_en3 /**< \brief Target EN3 */
691 } IfxMsc_Target;
692 
693 /** \brief Interrupt Control Register - Time Frame Interrupt Enable\n
694  * Definition in Ifx_MSC.ICR.B.TFIE
695  */
696 typedef enum
697 {
698  IfxMsc_TimeFrameInterrupt_disabled = 0, /**< \brief Interrupt generation disabled */
699  IfxMsc_TimeFrameInterrupt_enabled = 1 /**< \brief Interrupt generation enabled */
700 } IfxMsc_TimeFrameInterrupt;
701 
702 /** \brief Interrupt Control Register - Time Frame Interrupt Pointer\n
703  * Definition in Ifx_MSC.ICR.B.TFIP
704  */
705 typedef enum
706 {
707  IfxMsc_TimeFrameInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
708  IfxMsc_TimeFrameInterruptNode_SR1, /**< \brief Service request output SR1 selected */
709  IfxMsc_TimeFrameInterruptNode_SR2, /**< \brief Service request output SR2 selected */
710  IfxMsc_TimeFrameInterruptNode_SR3 /**< \brief Service request output SR3 selected */
711 } IfxMsc_TimeFrameInterruptNode;
712 
713 /** \brief Downstream Channel Transmission Mode\n
714  * Definition in Ifx_MSC.DSC.B.TM
715  */
716 typedef enum
717 {
718  IfxMsc_TransmissionMode_triggered = 0, /**< \brief Triggered Mode */
719  IfxMsc_TransmissionMode_dataRepetition = 1 /**< \brief Data Repetition Mode */
720 } IfxMsc_TransmissionMode;
721 
722 /** \brief Asynchronous Block Configuration Register - Underflow Interrupt Enable\n
723  * Definition in Ifx_MSC.ABC.B.UIE
724  */
725 typedef enum
726 {
727  IfxMsc_UnderflowInterrupt_disabled = 0, /**< \brief Disables the path of the Underflow interrupt towards the interrupt node */
728  IfxMsc_UnderflowInterrupt_enabled = 1 /**< \brief Enables the path of the Underflow interrupt towards the interrupt node */
729 } IfxMsc_UnderflowInterrupt;
730 
731 /** \brief Asynchronous Block Configuration Register - Underflow Interrupt Node Pointer\n
732  * Definition in Ifx_MSC.ABC.B.UIP
733  */
734 typedef enum
735 {
736  IfxMsc_UnderflowInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
737  IfxMsc_UnderflowInterruptNode_SR1, /**< \brief Service request output SR1 selected */
738  IfxMsc_UnderflowInterruptNode_SR2, /**< \brief Service request output SR2 selected */
739  IfxMsc_UnderflowInterruptNode_SR3, /**< \brief Service request output SR3 selected */
740  IfxMsc_UnderflowInterruptNode_SR4 /**< \brief Service request output SR4 selected */
741 } IfxMsc_UnderflowInterruptNode;
742 
743 /** \brief Channel Frame Type\n
744  * Definition in Ifx_MSC.USR.B.UFT
745  */
746 typedef enum
747 {
748  IfxMsc_UpstreamChannelFrameType_12bit = 0, /**< \brief 12-bit Upstream frame selected */
749  IfxMsc_UpstreamChannelFrameType_16bit = 1 /**< \brief 16-bit Upstream frame selected */
750 } IfxMsc_UpstreamChannelFrameType;
751 
752 /** \brief Upstream Receiving Rate\n
753  * Definition in Ifx_MSC.USR.B.URR
754  */
755 typedef enum
756 {
757  IfxMsc_UpstreamChannelReceivingRate_disabled = 0, /**< \brief Disabled */
758  IfxMsc_UpstreamChannelReceivingRate_4 = 1, /**< \brief Baud rate = f_MSC / 4 */
759  IfxMsc_UpstreamChannelReceivingRate_8 = 2, /**< \brief Baud rate = f_MSC / 8 */
760  IfxMsc_UpstreamChannelReceivingRate_16 = 3, /**< \brief Baud rate = f_MSC / 16 */
761  IfxMsc_UpstreamChannelReceivingRate_32 = 4, /**< \brief Baud rate = f_MSC / 32 */
762  IfxMsc_UpstreamChannelReceivingRate_64 = 5, /**< \brief Baud rate = f_MSC / 64 */
763  IfxMsc_UpstreamChannelReceivingRate_128 = 6, /**< \brief Baud rate = f_MSC / 128 */
764  IfxMsc_UpstreamChannelReceivingRate_256 = 7 /**< \brief Baud rate = f_MSC / 256 */
765 } IfxMsc_UpstreamChannelReceivingRate;
766 
767 /** \brief Upstream Control Enhanced Register 1 - Upstream Timeout Interrupt Enable\n
768  * Definition in Ifx_MSC.USCE.B.USTOEN
769  */
770 typedef enum
771 {
772  IfxMsc_UpstreamTimeoutInterrupt_disabled = 0, /**< \brief Upstream Timeout Interrupt Disabled */
773  IfxMsc_UpstreamTimeoutInterrupt_enabled = 1 /**< \brief Upstream Timeout Interrupt Enabled */
774 } IfxMsc_UpstreamTimeoutInterrupt;
775 
776 /** \brief Upstream Control Enhanced Register 1 - Upstream Timeout Interrupt Node Pointer\n
777  * Definition in Ifx_MSC.USCE.B.USTOIP
778  */
779 typedef enum
780 {
781  IfxMsc_UpstreamTimeoutInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
782  IfxMsc_UpstreamTimeoutInterruptNode_SR1, /**< \brief Service request output SR1 selected */
783  IfxMsc_UpstreamTimeoutInterruptNode_SR2, /**< \brief Service request output SR2 selected */
784  IfxMsc_UpstreamTimeoutInterruptNode_SR3 /**< \brief Service request output SR3 selected */
785 } IfxMsc_UpstreamTimeoutInterruptNode;
786 
787 /** \brief Upstream Control Enhanced Register 1 - Upstream Timeout Prescaler\n
788  * Definition in Ifx_MSC.USCE.B.USTOPRE
789  */
790 typedef enum
791 {
792  IfxMsc_UpstreamTimeoutPrescaler_1 = 0, /**< \brief Prescale value 1 for the upstream time-out limit */
793  IfxMsc_UpstreamTimeoutPrescaler_2 = 1, /**< \brief Prescale value 2 for the upstream time-out limit */
794  IfxMsc_UpstreamTimeoutPrescaler_4 = 2, /**< \brief Prescale value 4 for the upstream time-out limit */
795  IfxMsc_UpstreamTimeoutPrescaler_8 = 3, /**< \brief Prescale value 8 for the upstream time-out limit */
796  IfxMsc_UpstreamTimeoutPrescaler_16 = 4, /**< \brief Prescale value 16 for the upstream time-out limit */
797  IfxMsc_UpstreamTimeoutPrescaler_32 = 5, /**< \brief Prescale value 32 for the upstream time-out limit */
798  IfxMsc_UpstreamTimeoutPrescaler_64 = 6, /**< \brief Prescale value 64 for the upstream time-out limit */
799  IfxMsc_UpstreamTimeoutPrescaler_128 = 7, /**< \brief Prescale value 128 for the upstream time-out limit */
800  IfxMsc_UpstreamTimeoutPrescaler_256 = 8, /**< \brief Prescale value 256 for the upstream time-out limit */
801  IfxMsc_UpstreamTimeoutPrescaler_512 = 9, /**< \brief Prescale value 512 for the upstream time-out limit */
802  IfxMsc_UpstreamTimeoutPrescaler_1024 = 10, /**< \brief Prescale value 1024 for the upstream time-out limit */
803  IfxMsc_UpstreamTimeoutPrescaler_2048 = 11, /**< \brief Prescale value 2048 for the upstream time-out limit */
804  IfxMsc_UpstreamTimeoutPrescaler_4096 = 12, /**< \brief Prescale value 4096 for the upstream time-out limit */
805  IfxMsc_UpstreamTimeoutPrescaler_8192 = 13, /**< \brief Prescale value 8192 for the upstream time-out limit */
806  IfxMsc_UpstreamTimeoutPrescaler_16384 = 14, /**< \brief Prescale value 16384 for the upstream time-out limit */
807  IfxMsc_UpstreamTimeoutPrescaler_32768 = 15 /**< \brief Prescale value 32768 for the upstream time-out limit */
808 } IfxMsc_UpstreamTimeoutPrescaler;
809 
810 /** \brief Upstream Control Enhanced Register 1 - Upstream Timeout Value\n
811  * Definition in Ifx_MSC.USCE.B.USTOVAL
812  */
813 typedef enum
814 {
815  IfxMsc_UpstreamTimeoutValue_1 = 0, /**< \brief Upstream timeout value for the N-Divider */
816  IfxMsc_UpstreamTimeoutValue_2, /**< \brief Upstream timeout value for the N-Divider */
817  IfxMsc_UpstreamTimeoutValue_3, /**< \brief Upstream timeout value for the N-Divider */
818  IfxMsc_UpstreamTimeoutValue_4, /**< \brief Upstream timeout value for the N-Divider */
819  IfxMsc_UpstreamTimeoutValue_5, /**< \brief Upstream timeout value for the N-Divider */
820  IfxMsc_UpstreamTimeoutValue_6, /**< \brief Upstream timeout value for the N-Divider */
821  IfxMsc_UpstreamTimeoutValue_7, /**< \brief Upstream timeout value for the N-Divider */
822  IfxMsc_UpstreamTimeoutValue_8, /**< \brief Upstream timeout value for the N-Divider */
823  IfxMsc_UpstreamTimeoutValue_9, /**< \brief Upstream timeout value for the N-Divider */
824  IfxMsc_UpstreamTimeoutValue_10, /**< \brief Upstream timeout value for the N-Divider */
825  IfxMsc_UpstreamTimeoutValue_11, /**< \brief Upstream timeout value for the N-Divider */
826  IfxMsc_UpstreamTimeoutValue_12, /**< \brief Upstream timeout value for the N-Divider */
827  IfxMsc_UpstreamTimeoutValue_13, /**< \brief Upstream timeout value for the N-Divider */
828  IfxMsc_UpstreamTimeoutValue_14, /**< \brief Upstream timeout value for the N-Divider */
829  IfxMsc_UpstreamTimeoutValue_15, /**< \brief Upstream timeout value for the N-Divider */
830  IfxMsc_UpstreamTimeoutValue_16 /**< \brief Upstream timeout value for the N-Divider */
831 } IfxMsc_UpstreamTimeoutValue;
832 
833 /** \} */
834 
835 /** \addtogroup IfxLld_Msc_Std_Config_Flags
836  * \{ */
837 
838 /******************************************************************************/
839 /*-------------------------Inline Function Prototypes-------------------------*/
840 /******************************************************************************/
841 
842 /** \brief Clear ABRA overflow flag
843  * \param msc pointer to the base of MSC registers
844  * \return None
845  */
846 IFX_INLINE void IfxMsc_clearAbraOverflowFlag(Ifx_MSC *msc);
847 
848 /** \brief Clear ABRA underflow flag
849  * \param msc pointer to the base of MSC registers
850  * \return None
851  */
852 IFX_INLINE void IfxMsc_clearAbraUnderflowFlag(Ifx_MSC *msc);
853 
854 /** \brief Clear Upstream timeout
855  * \param msc pointer to the base of MSC registers
856  * \return None
857  */
858 IFX_INLINE void IfxMsc_clearUpstreamTimeout(Ifx_MSC *msc);
859 
860 /** \brief Clear the valid flag
861  * \param msc pointer to the base of MSC registers
862  * \param upstreamIdx data register ID
863  * \return None
864  */
865 IFX_INLINE void IfxMsc_clearUpstreamValidFlag(Ifx_MSC *msc, uint8 upstreamIdx);
866 
867 /** \brief Get the status of the valid flag
868  * \param msc pointer to the base of MSC registers
869  * \param upstreamIdx data register ID
870  * \return Status TRUE or FALSE
871  */
872 IFX_INLINE boolean IfxMsc_getUpstreamValidFlag(Ifx_MSC *msc, uint8 upstreamIdx);
873 
874 /** \} */
875 
876 /** \addtogroup IfxLld_Msc_Std_Set_Command_Target
877  * \{ */
878 
879 /******************************************************************************/
880 /*-------------------------Inline Function Prototypes-------------------------*/
881 /******************************************************************************/
882 
883 /** \brief Select the target for command phase
884  * \param msc pointer to the base of MSC registers
885  * \param enX Target to be selected
886  * \return None
887  */
888 IFX_INLINE void IfxMsc_setCommandTarget(Ifx_MSC *msc, IfxMsc_Target enX);
889 
890 /** \} */
891 
892 /** \addtogroup IfxLld_Msc_Std_Set_Data
893  * \{ */
894 
895 /******************************************************************************/
896 /*-------------------------Inline Function Prototypes-------------------------*/
897 /******************************************************************************/
898 
899 /** \brief Select the target for data high phase
900  * \param msc pointer to the base of MSC registers
901  * \param enX Target to be selected
902  * \return None
903  */
904 IFX_INLINE void IfxMsc_setDataHighTarget(Ifx_MSC *msc, IfxMsc_Target enX);
905 
906 /** \brief Select the target for data low phase
907  * \param msc pointer to the base of MSC registers
908  * \param enX Target to be selected
909  * \return None
910  */
911 IFX_INLINE void IfxMsc_setDataLowTarget(Ifx_MSC *msc, IfxMsc_Target enX);
912 
913 /** \} */
914 
915 /** \addtogroup IfxLld_Msc_Std_Get_Data
916  * \{ */
917 
918 /******************************************************************************/
919 /*-------------------------Inline Function Prototypes-------------------------*/
920 /******************************************************************************/
921 
922 /** \brief Get the upstream data from upstream data register
923  * \param msc pointer to the base of MSC registers
924  * \param upstreamIdx Upstream data register ID
925  * \return Recevived data
926  */
927 IFX_INLINE uint16 IfxMsc_getData(Ifx_MSC *msc, uint8 upstreamIdx);
928 
929 /** \brief Get the selected target during high phase
930  * \param msc pointer to the base of MSC registers
931  * \return Selected target
932  */
933 IFX_INLINE IfxMsc_Target IfxMsc_getDataHighTarget(Ifx_MSC *msc);
934 
935 /** \brief Get the selected target during low phase
936  * \param msc pointer to the base of MSC registers
937  * \return Selected target
938  */
939 IFX_INLINE IfxMsc_Target IfxMsc_getDataLowTarget(Ifx_MSC *msc);
940 
941 /** \} */
942 
943 /** \addtogroup IfxLld_Msc_Std_Enable_Module
944  * \{ */
945 
946 /******************************************************************************/
947 /*-------------------------Global Function Prototypes-------------------------*/
948 /******************************************************************************/
949 
950 /** \brief Enable MSC kernel
951  * \param msc pointer to the base of MSC registers
952  * \return None
953  */
954 IFX_EXTERN void IfxMsc_enableModule(Ifx_MSC *msc);
955 
956 /** \} */
957 
958 /** \addtogroup IfxLld_Msc_Std_Reset_Module
959  * \{ */
960 
961 /******************************************************************************/
962 /*-------------------------Global Function Prototypes-------------------------*/
963 /******************************************************************************/
964 
965 /** \brief Clear reset bit of MSC kernel
966  * \param msc pointer to the base of MSC registers
967  * \return None
968  */
969 IFX_EXTERN void IfxMsc_clearReset(Ifx_MSC *msc);
970 
971 /** \brief Reset MSC kernel
972  * \param msc pointer to the base of MSC registers
973  * \return None
974  */
975 IFX_EXTERN void IfxMsc_resetModule(Ifx_MSC *msc);
976 
977 /** \} */
978 
979 /** \addtogroup IfxLld_Msc_Std_Baud_Calculator
980  * \{ */
981 
982 /******************************************************************************/
983 /*-------------------------Global Function Prototypes-------------------------*/
984 /******************************************************************************/
985 
986 /** \brief Get the NDD value for the supplied baud rate when when ABRA block is enabled
987  * \param baud Required baud rate
988  * \return NDD value
989  */
990 IFX_EXTERN uint32 IfxMsc_downstreamAbraBaudCalculator(uint32 baud);
991 
992 /** \brief Get the step value for the supplied baud rate when divider mode is fractional
993  * \param msc pointer to the base of MSC registers
994  * \param baud Required baud rate
995  * \return Step value
996  */
997 IFX_EXTERN uint64 IfxMsc_upstreamFractionalBaudCalculator(Ifx_MSC *msc, uint32 baud);
998 
999 /** \brief Get the step value for the supplied baud rate when divider mode is normal
1000  * \param msc pointer to the base of MSC registers
1001  * \param baud Required baud rate
1002  * \return Step value
1003  */
1004 IFX_EXTERN uint32 IfxMsc_upstreamNormalBaudCalculator(Ifx_MSC *msc, uint32 baud);
1005 
1006 /** \} */
1007 
1008 /** \addtogroup IfxLld_Msc_Std_IO
1009  * \{ */
1010 
1011 /******************************************************************************/
1012 /*-------------------------Inline Function Prototypes-------------------------*/
1013 /******************************************************************************/
1014 
1015 /** \brief Initializes a EN output
1016  * \param en the EN Pin which should be configured
1017  * \param pinMode the pin output mode which should be configured
1018  * \param padDriver the pad driver mode which should be configured
1019  * \return None
1020  */
1021 IFX_INLINE void IfxMsc_initEnPin(const IfxMsc_En_Out *en, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver);
1022 
1023 /** \brief Initializes a FCLN output
1024  * \param fcln the FCLN Pin which should be configured
1025  * \param pinMode the pin output mode which should be configured
1026  * \param padDriver the pad driver mode which should be configured
1027  * \return None
1028  */
1029 IFX_INLINE void IfxMsc_initFclnPin(const IfxMsc_Fcln_Out *fcln, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver);
1030 
1031 /** \brief Initializes a FCLP output
1032  * \param fclp the FCLP Pin which should be configured
1033  * \param pinMode the pin output mode which should be configured
1034  * \param padDriver the pad driver mode which should be configured
1035  * \return None
1036  */
1037 IFX_INLINE void IfxMsc_initFclpPin(const IfxMsc_Fclp_Out *fclp, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver);
1038 
1039 /** \brief Initializes a INJ input
1040  * \param inj the INJ Pin which should be configured
1041  * \param pinMode the pin input mode which should be configured
1042  * \return None
1043  */
1044 IFX_INLINE void IfxMsc_initInjPin(const IfxMsc_Inj_In *inj, IfxPort_InputMode pinMode);
1045 
1046 /** \brief Initializes a SDI input
1047  * \param sdi the SDI Pin which should be configured
1048  * \param pinMode the pin input mode which should be configured
1049  * \return None
1050  */
1051 IFX_INLINE void IfxMsc_initSdiPin(const IfxMsc_Sdi_In *sdi, IfxPort_InputMode pinMode);
1052 
1053 /** \brief Initializes a SON output
1054  * \param son the SON Pin which should be configured
1055  * \param pinMode the pin output mode which should be configured
1056  * \param padDriver the pad driver mode which should be configured
1057  * \return None
1058  */
1059 IFX_INLINE void IfxMsc_initSonPin(const IfxMsc_Son_Out *son, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver);
1060 
1061 /** \brief Initializes a SOP output
1062  * \param sop the SOP Pin which should be configured
1063  * \param pinMode the pin output mode which should be configured
1064  * \param padDriver the pad driver mode which should be configured
1065  * \return None
1066  */
1067 IFX_INLINE void IfxMsc_initSopPin(const IfxMsc_Sop_Out *sop, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver);
1068 
1069 /** \} */
1070 
1071 /******************************************************************************/
1072 /*-------------------------Inline Function Prototypes-------------------------*/
1073 /******************************************************************************/
1074 
1075 /** \brief Sets the sensitivity of the module to sleep signal
1076  * \param msc pointer to MSC registers
1077  * \param mode mode selection (enable/disable)
1078  * \return None
1079  */
1080 IFX_INLINE void IfxMsc_setSleepMode(Ifx_MSC *msc, IfxMsc_SleepMode mode);
1081 
1082 /******************************************************************************/
1083 /*-------------------------Global Function Prototypes-------------------------*/
1084 /******************************************************************************/
1085 
1086 /** \brief clear data frame interrupt flag
1087  * \param msc pointer to the base of MSC registers
1088  * \return None
1089  */
1090 IFX_EXTERN void IfxMsc_clearDataFrameInterruptFlag(Ifx_MSC *msc);
1091 
1092 /** \brief get the status of the active data frame
1093  * \param msc pointer to the base of MSC registers
1094  * \return Status TRUE or FALSE
1095  */
1096 IFX_EXTERN boolean IfxMsc_getActiveDataFrameStatus(Ifx_MSC *msc);
1097 
1098 /** \brief get the status of the data frame interrupt flag
1099  * \param msc pointer to the base of MSC registers
1100  * \return Status TRUE or FALSE
1101  */
1102 IFX_EXTERN boolean IfxMsc_getDataFrameInterruptFlag(Ifx_MSC *msc);
1103 
1104 /******************************************************************************/
1105 /*---------------------Inline Function Implementations------------------------*/
1106 /******************************************************************************/
1107 
1108 IFX_INLINE void IfxMsc_clearAbraOverflowFlag(Ifx_MSC *msc)
1109 {
1110  /* Overflow Flag Clear */
1111  msc->ABC.B.OFM = 2;
1112 }
1113 
1114 
1115 IFX_INLINE void IfxMsc_clearAbraUnderflowFlag(Ifx_MSC *msc)
1116 {
1117  /* Underflow Flag Clear */
1118  msc->ABC.B.UFM = 2;
1119 }
1120 
1121 
1122 IFX_INLINE void IfxMsc_clearUpstreamTimeout(Ifx_MSC *msc)
1123 {
1124  /* Upstream Timeout Clear */
1125  msc->USCE.B.USTC = 1;
1126 }
1127 
1128 
1129 IFX_INLINE void IfxMsc_clearUpstreamValidFlag(Ifx_MSC *msc, uint8 upstreamIdx)
1130 {
1131  msc->UD[upstreamIdx].B.C = 1;
1132 }
1133 
1134 
1135 IFX_INLINE uint16 IfxMsc_getData(Ifx_MSC *msc, uint8 upstreamIdx)
1136 {
1137  uint16 data = 0;
1138 
1139  data = msc->UD[upstreamIdx].B.DATA;
1140 
1141  return data;
1142 }
1143 
1144 
1145 IFX_INLINE IfxMsc_Target IfxMsc_getDataHighTarget(Ifx_MSC *msc)
1146 {
1147  /* get data high target - en0, en1, en2 or en3 */
1148  return (IfxMsc_Target)msc->OCR.B.CSH;
1149 }
1150 
1151 
1152 IFX_INLINE IfxMsc_Target IfxMsc_getDataLowTarget(Ifx_MSC *msc)
1153 {
1154  /* get data low target - en0, en1, en2 or en3 */
1155  return (IfxMsc_Target)msc->OCR.B.CSL;
1156 }
1157 
1158 
1159 IFX_INLINE boolean IfxMsc_getUpstreamValidFlag(Ifx_MSC *msc, uint8 upstreamIdx)
1160 {
1161  boolean flag = 0;
1162 
1163  flag = msc->UD[upstreamIdx].B.V;
1164 
1165  return flag;
1166 }
1167 
1168 
1169 IFX_INLINE void IfxMsc_initEnPin(const IfxMsc_En_Out *en, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver)
1170 {
1171  IfxPort_setPinModeOutput(en->pin.port, en->pin.pinIndex, pinMode, en->select);
1172  IfxPort_setPinPadDriver(en->pin.port, en->pin.pinIndex, padDriver);
1173 }
1174 
1175 
1176 IFX_INLINE void IfxMsc_initFclnPin(const IfxMsc_Fcln_Out *fcln, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver)
1177 {
1178  IfxPort_setPinModeOutput(fcln->pin.port, fcln->pin.pinIndex, pinMode, fcln->select);
1179  IfxPort_setPinPadDriver(fcln->pin.port, fcln->pin.pinIndex, padDriver);
1180 }
1181 
1182 
1183 IFX_INLINE void IfxMsc_initFclpPin(const IfxMsc_Fclp_Out *fclp, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver)
1184 {
1185  IfxPort_setPinModeOutput(fclp->pin.port, fclp->pin.pinIndex, pinMode, fclp->select);
1186  IfxPort_setPinPadDriver(fclp->pin.port, fclp->pin.pinIndex, padDriver);
1187 }
1188 
1189 
1190 IFX_INLINE void IfxMsc_initInjPin(const IfxMsc_Inj_In *inj, IfxPort_InputMode pinMode)
1191 {
1192  IfxPort_setPinModeInput(inj->pin.port, inj->pin.pinIndex, pinMode);
1193 }
1194 
1195 
1196 IFX_INLINE void IfxMsc_initSdiPin(const IfxMsc_Sdi_In *sdi, IfxPort_InputMode pinMode)
1197 {
1198  IfxPort_setPinModeInput(sdi->pin.port, sdi->pin.pinIndex, pinMode);
1199  sdi->module->OCR.B.SDISEL = sdi->select;
1200 }
1201 
1202 
1203 IFX_INLINE void IfxMsc_initSonPin(const IfxMsc_Son_Out *son, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver)
1204 {
1205  IfxPort_setPinModeOutput(son->pin.port, son->pin.pinIndex, pinMode, son->select);
1206  IfxPort_setPinPadDriver(son->pin.port, son->pin.pinIndex, padDriver);
1207 }
1208 
1209 
1210 IFX_INLINE void IfxMsc_initSopPin(const IfxMsc_Sop_Out *sop, IfxPort_OutputMode pinMode, IfxPort_PadDriver padDriver)
1211 {
1212  IfxPort_setPinModeOutput(sop->pin.port, sop->pin.pinIndex, pinMode, sop->select);
1213  IfxPort_setPinPadDriver(sop->pin.port, sop->pin.pinIndex, padDriver);
1214 }
1215 
1216 
1217 IFX_INLINE void IfxMsc_setCommandTarget(Ifx_MSC *msc, IfxMsc_Target enX)
1218 {
1219  /* Set command target - en0, en1, en2 or en3 */
1220  msc->OCR.B.CSC = enX;
1221 }
1222 
1223 
1224 IFX_INLINE void IfxMsc_setDataHighTarget(Ifx_MSC *msc, IfxMsc_Target enX)
1225 {
1226  /* Set data high target - en0, en1, en2 or en3 */
1227  msc->OCR.B.CSH = enX;
1228 }
1229 
1230 
1231 IFX_INLINE void IfxMsc_setDataLowTarget(Ifx_MSC *msc, IfxMsc_Target enX)
1232 {
1233  /* Set data low target - en0, en1, en2 or en3 */
1234  msc->OCR.B.CSL = enX;
1235 }
1236 
1237 
1238 IFX_INLINE void IfxMsc_setSleepMode(Ifx_MSC *msc, IfxMsc_SleepMode mode)
1239 {
1240  uint16 passwd = IfxScuWdt_getCpuWatchdogPassword();
1241  IfxScuWdt_clearCpuEndinit(passwd);
1242  msc->CLC.B.EDIS = mode;
1243  IfxScuWdt_setCpuEndinit(passwd);
1244 }
1245 
1246 
1247 #endif /* IFXMSC_H */