7 * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8 *
9 *
10 * IMPORTANT NOTICE
11 *
12 *
13 * Infineon Technologies AG (Infineon) is supplying this file for use
14 * exclusively with Infineon's microcontroller products. This file can be freely
15 * distributed within development tools that are supporting such microcontroller
16 * products.
17 *
18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21 * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23 *
24 *
25 * \defgroup IfxLld_Scu SCU
26 * \addtogroup IfxLld_Scu
27 * \{
28 * \defgroup IfxLld_ScuCcu How to use the Scu Clock driver?
29 * \addtogroup IfxLld_ScuCcu
30 * \{
31 *
32 * The Scu Clock control unit driver provides a default configuration for pll and Clock initialisation and set of peripheral clock configuration functions.
33 *
34 * In the following sections it will be described, how to integrate the driver into the application framework.
806/** \brief API to get actual PLL2 (K3 Divider for ADC clock) frequency
807 * This API returns the PLL2ERAY frequency based on the K3 divider value in PLLERAYCON and the VCO frequency. This frequency is one of the configurable inputs to ADC clock.
808 * \return PLL2ERAY (K3 Divider for ADC clock) frequency in Hz
812/** \brief API to get actual PLL2 (K3 Divider for ADC clock) frequency
813 * This API returns the PLL2 frequency based on the K3 divider value in PLLCON and the VCO frequency. This frequency is one of the configurable inputs to ADC clock.
814 * \return PLL2 (K3 Divider for ADC clock) frequency in Hz