iLLD_TC27xD  1.0
Macros | Enumerations
IfxScu_cfg.h File Reference
SCU

SCU on-chip implementation data. More...

#include "Ifx_Cfg.h"
#include "IfxScu_bf.h"
#include "IfxFlash_bf.h"

Go to the source code of this file.

Macros

#define IFX_CFG_SCU_XTAL_FREQUENCY   20000000
 Default External oscillator frequency. More...
 
#define IFX_CFG_SCU_PLL_FREQUENCY   200000000
 Default PLL frequency. More...
 
#define IFXSCU_VCO_BASE_FREQUENCY   (100000000.0)
 
#define IFXSCU_EVR_OSC_FREQUENCY   (100000000.0)
 
#define IFXSCU_PLL_FREERUNNING_FREQUENCY   (100000000.0)
 
#define IFXSCU_CFG_PLL_STEPS_16MHZ_80MHZ
 Macros to configure Pll steps, Macros to configure the Pll steps for different profiles of Crystal frequency and target frequencies. This configuration is important for the current jump controll during clock throttling. IfxScu_PllStepsConfig. More...
 
#define IFXSCU_CFG_PLL_STEPS_16MHZ_133MHZ
 Macro for Pll step for profile with 16MHz Crystal and 133MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_16MHZ_160MHZ
 Macro for Pll step for profile with 16MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_16MHZ_200MHZ
 Macro for Pll step for profile with 16MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_16MHZ_240MHZ
 Macro for Pll step for profile with 16MHz Crystal and 240MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_20MHZ_80MHZ
 Macro for Pll step for profile with 20MHz Crystal and 80MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_20MHZ_133MHZ
 Macro for Pll step for profile with 20MHz Crystal and 133MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_20MHZ_160MHZ
 Macro for Pll step for profile with 20MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_20MHZ_200MHZ
 Macro for Pll step for profile with 20MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_20MHZ_240MHZ
 Macro for Pll step for profile with 20MHz Crystal and 240MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_20MHZ_300MHZ
 Macro for Pll step for profile with 20MHz Crystal and 300MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_40MHZ_80MHZ
 Macro for Pll step for profile with 40MHz Crystal and 80MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_40MHZ_133MHZ
 Macro for Pll step for profile with 40MHz Crystal and 133MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_40MHZ_160MHZ
 Macro for Pll step for profile with 40MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_40MHZ_200MHZ
 Macro for Pll step for profile with 40MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_40MHZ_240MHZ
 Macro for Pll step for profile with 40MHz Crystal and 240MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_40MHZ_300MHZ
 Macro for Pll step for profile with 40MHz Crystal and 300MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_8MHZ_80MHZ
 Macro for Pll step for profile with 8MHz Crystal and 80MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_8MHZ_160MHZ
 Macro for Pll step for profile with 8MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_8MHZ_200MHZ
 Macro for Pll step for profile with 8MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_80MHZ
 Macros to configure Initial Pll step. Macros to configure the Pll initial step, where the configuration of PDIV, NDIV and K2DIV are done for the internal Oscillator frequency. IfxScu_InitialStepConfig. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_133MHZ
 Macro for Initial Pll step, for profile with 16MHz Crystal and 133MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_160MHZ
 Macro for Initial Pll step, for profile with 16MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_200MHZ
 Macro for Initial Pll step, for profile with 16MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_240MHZ
 Macro for Initial Pll step, for profile with 16MHz Crystal and 240MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_80MHZ
 Macro for Initial Pll step, for profile with 20MHz Crystal and 80MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_133MHZ
 Macro for Initial Pll step, for profile with 20MHz Crystal and 133MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_160MHZ
 Macro for Initial Pll step, for profile with 20MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_200MHZ
 Macro for Initial Pll step, for profile with 20MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_240MHZ
 Macro for Initial Pll step, for profile with 20MHz Crystal and 240MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_300MHZ
 Macro for Initial Pll step, for profile with 20MHz Crystal and 300MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_80MHZ
 Macro for Initial Pll step, for profile with 40MHz Crystal and 80MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_133MHZ
 Macro for Initial Pll step, for profile with 40MHz Crystal and 133MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_160MHZ
 Macro for Initial Pll step, for profile with 40MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_200MHZ
 Macro for Initial Pll step, for profile with 40MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_240MHZ
 Macro for Initial Pll step, for profile with 40MHz Crystal and 240MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_300MHZ
 Macro for Initial Pll step, for profile with 40MHz Crystal and 300MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_80MHZ
 Macro for Initial Pll step, for profile with 8MHz Crystal and 80MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_160MHZ
 Macro for Initial Pll step, for profile with 8MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_200MHZ
 Macro for Initial Pll step, for profile with 8MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_MAXDIV_80MHZ   (1)
 Macros to configure CCUCON registers. Macros to configure the Pll initial step, where the configuration of PDIV, NDIV and K2DIV are done for the internal Oscillator frequency. IfxScu_InitialStepConfig. More...
 
#define IFXSCU_CFG_MAXDIV_133MHZ   (1)
 Macro to configure MAXDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_MAXDIV_160MHZ   (1)
 Macro to configure MAXDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_MAXDIV_200MHZ   (1)
 Macro to configure MAXDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_MAXDIV_240MHZ   (1)
 Macro to configure MAXDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_MAXDIV_300MHZ   (1)
 Macro to configure MAXDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_SRIDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
 Macro to configure SRIDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_SRIDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
 Macro to configure SRIDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_SRIDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
 Macro to configure SRIDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_SRIDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
 Macro to configure SRIDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_SRIDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
 Macro to configure SRIDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_SRIDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
 Macro to configure SRIDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD1DIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure BAUD1DIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD1DIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure BAUD1DIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD1DIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure BAUD1DIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD1DIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure BAUD1DIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD1DIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure BAUD1DIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD1DIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure BAUD1DIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD2DIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
 Macro to configure BAUD2DIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD2DIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
 Macro to configure BAUD2DIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD2DIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
 Macro to configure BAUD2DIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD2DIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
 Macro to configure BAUD2DIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD2DIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
 Macro to configure BAUD2DIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD2DIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
 Macro to configure BAUD2DIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_SPBDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ * 2) /*Max: 100MHz */
 Macro to configure SPBDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_SPBDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure SPBDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_SPBDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure SPBDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_SPBDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure SPBDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_SPBDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure SPBDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_SPBDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure SPBDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_FSI2DIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
 Macro to configure FSI2DIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_FSI2DIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
 Macro to configure FSI2DIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_FSI2DIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
 Macro to configure FSI2DIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_FSI2DIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
 Macro to configure FSI2DIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_FSI2DIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
 Macro to configure FSI2DIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_FSI2DIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
 Macro to configure FSI2DIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_FSIDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure FSIDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_FSIDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure FSIDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_FSIDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure FSIDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_FSIDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure FSIDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_FSIDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure FSIDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_FSIDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure FSIDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_CANDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure CANDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_CANDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure CANDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_CANDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure CANDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_CANDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure CANDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_CANDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure CANDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_CANDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure CANDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_ERAYDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 80MHz */
 Macro to configure ERAYDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_ERAYDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 80MHz */
 Macro to configure ERAYDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_ERAYDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 80MHz */
 Macro to configure ERAYDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_ERAYDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 3) /*Max: 80MHz */
 Macro to configure ERAYDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_ERAYDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 80MHz */
 Macro to configure ERAYDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_ERAYDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 4) /*Max: 80MHz */
 Macro to configure ERAYDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_STMDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure STMDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_STMDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure STMDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_STMDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure STMDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_STMDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure STMDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_STMDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure STMDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_STMDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure STMDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_GTMDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure GTMDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_GTMDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure GTMDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_GTMDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure GTMDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_GTMDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure GTMDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_GTMDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure GTMDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_GTMDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure GTMDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_ETHDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ * 2)
 Macro to configure ETHDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_ETHDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 3)
 Macro to configure ETHDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_ETHDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 4)
 Macro to configure ETHDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_ETHDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 4)
 Macro to configure ETHDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_ETHDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 5)
 Macro to configure ETHDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_ETHDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 6)
 Macro to configure ETHDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINFDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
 Macro to configure ASCLINFDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINFDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
 Macro to configure ASCLINFDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINFDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
 Macro to configure ASCLINFDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINFDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
 Macro to configure ASCLINFDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINFDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
 Macro to configure ASCLINFDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINFDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
 Macro to configure ASCLINFDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINSDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure ASCLINSDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINSDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure ASCLINSDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINSDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure ASCLINSDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINSDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure ASCLINSDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINSDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure ASCLINSDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINSDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure ASCLINSDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_BBBDIV_80MHZ   (IFXSCU_CFG_SRIDIV_80MHZ * 2)
 Macro to configure BBBDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_BBBDIV_133MHZ   (IFXSCU_CFG_SRIDIV_133MHZ * 2)
 Macro to configure BBBDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_BBBDIV_160MHZ   (IFXSCU_CFG_SRIDIV_160MHZ * 2)
 Macro to configure BBBDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_BBBDIV_200MHZ   (IFXSCU_CFG_SRIDIV_200MHZ * 2)
 Macro to configure BBBDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_BBBDIV_240MHZ   (IFXSCU_CFG_SRIDIV_240MHZ * 2)
 Macro to configure BBBDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_BBBDIV_300MHZ   (IFXSCU_CFG_SRIDIV_300MHZ * 2)
 Macro to configure BBBDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_CPU0DIV_80MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU0DIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_CPU0DIV_133MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU0DIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_CPU0DIV_160MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU0DIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_CPU0DIV_200MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU0DIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_CPU0DIV_240MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU0DIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_CPU0DIV_300MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU0DIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_CPU1DIV_80MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU1DIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_CPU1DIV_133MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU1DIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_CPU1DIV_160MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU1DIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_CPU1DIV_200MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU1DIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_CPU1DIV_240MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU1DIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_CPU1DIV_300MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU1DIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_CPU2DIV_80MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU2DIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_CPU2DIV_133MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU2DIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_CPU2DIV_160MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU2DIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_CPU2DIV_200MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU2DIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_CPU2DIV_240MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU2DIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_CPU2DIV_300MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU2DIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_80MHZ   (3 - 1)
 Macros to configure FLASH.FCON register for flash waitstate configuration. IfxScu_InitialStepConfig. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_133MHZ   (4 - 1)
 Macro to configure FCON.WSPFLASH at 133MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_160MHZ   (5 - 1)
 Macro to configure FCON.WSPFLASH at 160MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_200MHZ   (6 - 1)
 Macro to configure FCON.WSPFLASH at 200MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_240MHZ   (8 - 1)
 Macro to configure FCON.WSPFLASH at 240MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_300MHZ   (9 - 1)
 Macro to configure FCON.WSPFLASH at 300MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECPF_80MHZ   (1 - 1)
 Macro to configure FCON.WSECP_ at 80MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECPF_133MHZ   (2 - 1)
 Macro to configure FCON.WSECPF at 133MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECPF_160MHZ   (2 - 1)
 Macro to configure FCON.WSECPF at 160MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECPF_200MHZ   (2 - 1)
 Macro to configure FCON.WSECPF at 200MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECPF_240MHZ   (3 - 1)
 Macro to configure FCON.WSECPF_ at 240MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECPF_300MHZ   (3 - 1)
 Macro to configure FCON.WSECPF at 300MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_80MHZ   (16 - 1)
 Macro to configure FCON.WSDFLASH at 80MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_133MHZ   (14 - 1)
 Macro to configure FCON.WSDFLASH_ at 133MHz target frequency, where fSRI= 133/2= 66.5MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_160MHZ   (16 - 1)
 Macro to configure FCON.WSDFLASH at 160MHz target frequency, where fSRI= 160/2= 80MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_200MHZ   (20 - 1)
 Macro to configure FCON.WSDFLASH at 200MHz target frequency, where fSRI= 200/2= 100MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_240MHZ   (16 - 1)
 Macro to configure FCON.WSDFLASH at 240MHz target frequency, where fSRI= 240/3= 80MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_300MHZ   (20 - 1)
 Macro to configure FCON.WSDFLASH at 300MHz target frequency, where fSRI= 300/3= 100MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECDF_80MHZ   (2 - 1)
 Macro to configure FCON.WSECDF at 80MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECDF_133MHZ   (2 - 1)
 Macro to configure FCON.WSECDF at 133MHz target frequency, where fSRI= 133/2= 66.5MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECDF_160MHZ   (2 - 1)
 Macro to configure FCON.WSECDF at 160MHz target frequency, where fSRI= 160/2= 80MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECDF_200MHZ   (2 - 1)
 Macro to configure FCON.WSECDF at 200MHz target frequency, where fSRI= 200/2= 100MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECDF_240MHZ   (2 - 1)
 Macro to configure FCON.WSECDF at 240MHz target frequency, where fSRI= 240/3= 80MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECDF_300MHZ   (2 - 1)
 Macro to configure FCON.WSECDF at 300MHz target frequency, where fSRI= 300/3= 100MHZ. More...
 
#define IFXSCU_CFG_FLASH_WAITSTATE_MSK
 Macros to configure FLASH.FCON registers. More...
 
#define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_(pllFreq)
 
#define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC(pllFreq)   IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_(pllFreq)
 
#define IFXSCU_CFG_FLASH_WAITSTATE_VAL   IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON0_MASK
 Macros to configure CCUCON0 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON0_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON0_BASIC(pllFreq)   IFXSCU_CFG_CCUCON0_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON0   IFXSCU_CFG_CCUCON0_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON1_MASK
 Macros to configure CCUCON1 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON1_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON1_BASIC(pllFreq)   IFXSCU_CFG_CCUCON1_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON1   IFXSCU_CFG_CCUCON1_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON2_MASK
 Macros to configure CCUCON2 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON2_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON2_BASIC(pllFreq)   IFXSCU_CFG_CCUCON2_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON2   IFXSCU_CFG_CCUCON2_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON5_MASK
 Macros to configure CCUCON5 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON5_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON5_BASIC(pllFreq)   IFXSCU_CFG_CCUCON5_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON5   IFXSCU_CFG_CCUCON5_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON6_MASK
 Macros to configure CCUCON6 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON6_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON6_BASIC(pllFreq)   IFXSCU_CFG_CCUCON6_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON6   IFXSCU_CFG_CCUCON6_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON7_MASK
 Macros to configure CCUCON7 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON7_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON7_BASIC(pllFreq)   IFXSCU_CFG_CCUCON7_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON7   IFXSCU_CFG_CCUCON7_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON8_MASK
 Macros to configure CCUCON8 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON8_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON8_BASIC(pllFreq)   IFXSCU_CFG_CCUCON8_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON8   IFXSCU_CFG_CCUCON8_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CLK_DISTRIBUTION
 
#define IFXSCU_CFG_PLL_STEPS_BASIC_(xtalFreq, pllFreq)   IFXSCU_CFG_PLL_STEPS_##xtalFreq##_##pllFreq
 
#define IFXSCU_CFG_PLL_STEPS_BASIC(xtalFreq, pllFreq)   IFXSCU_CFG_PLL_STEPS_BASIC_(xtalFreq, pllFreq)
 
#define IFXSCU_CFG_PLL_STEPS   IFXSCU_CFG_PLL_STEPS_BASIC(IFXSCU_CFG_XTAL_FREQ, IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_(xtalFreq, pllFreq)   IFXSCU_CFG_PLL_INITIAL_STEP_##xtalFreq##_##pllFreq
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC(xtalFreq, pllFreq)   IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_(xtalFreq, pllFreq)
 
#define IFXSCU_CFG_PLL_INITIAL_STEP   IFXSCU_CFG_PLL_INITIAL_STEP_BASIC(IFXSCU_CFG_XTAL_FREQ, IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_FLASH_WAITSTATE
 
#define IFXSCU_CFG_XTAL_FREQ   20MHZ
 
#define IFXSCU_CFG_PLL_FREQ   200MHZ
 

Enumerations

enum  IfxScu_CCUCON0_CLKSEL {
  IfxScu_CCUCON0_CLKSEL_fBack = 0,
  IfxScu_CCUCON0_CLKSEL_fPll = 1
}
 
enum  IfxScu_CCUCON1_INSEL {
  IfxScu_CCUCON1_INSEL_fOsc1 = 0,
  IfxScu_CCUCON1_INSEL_fOsc0 = 1
}
 
enum  IfxScu_WDTCON1_IR {
  IfxScu_WDTCON1_IR_divBy16384 = 0,
  IfxScu_WDTCON1_IR_divBy256 = 1,
  IfxScu_WDTCON1_IR_divBy64 = 2
}
 
enum  IfxScu_PMCSR_REQSLP {
  IfxScu_PMCSR_REQSLP_Run = 0U,
  IfxScu_PMCSR_REQSLP_Idle = 1U,
  IfxScu_PMCSR_REQSLP_Sleep = 2U,
  IfxScu_PMCSR_REQSLP_Stby = 3U
}
 

Detailed Description

SCU on-chip implementation data.

Version
iLLD_1_0_0_11_0
Copyright
Copyright (c) 2012 Infineon Technologies AG. All rights reserved.
                            IMPORTANT NOTICE

Infineon Technologies AG (Infineon) is supplying this file for use exclusively with Infineon's microcontroller products. This file can be freely distributed within development tools that are supporting such microcontroller products.

THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

Definition in file IfxScu_cfg.h.

Macro Definition Documentation

#define IFX_CFG_SCU_PLL_FREQUENCY   200000000

Default PLL frequency.

Definition at line 49 of file IfxScu_cfg.h.

#define IFX_CFG_SCU_XTAL_FREQUENCY   20000000

Default External oscillator frequency.

Definition at line 43 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINFDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */

Macro to configure ASCLINFDIV at 133MHz target frequency.

Definition at line 925 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINFDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */

Macro to configure ASCLINFDIV at 160MHz target frequency.

Definition at line 930 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINFDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */

Macro to configure ASCLINFDIV at 200MHz target frequency.

Definition at line 935 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINFDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */

Macro to configure ASCLINFDIV at 240MHz target frequency.

Definition at line 940 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINFDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */

Macro to configure ASCLINFDIV at 300MHz target frequency.

Definition at line 945 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINFDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */

Macro to configure ASCLINFDIV at 80MHz target frequency.

Definition at line 920 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINSDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure ASCLINSDIV at 133MHz target frequency.

Definition at line 955 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINSDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure ASCLINSDIV at 160MHz target frequency.

Definition at line 960 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINSDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure ASCLINSDIV at 200MHz target frequency.

Definition at line 965 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINSDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure ASCLINSDIV at 240MHz target frequency.

Definition at line 970 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINSDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure ASCLINSDIV at 300MHz target frequency.

Definition at line 975 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINSDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure ASCLINSDIV at 80MHz target frequency.

Definition at line 950 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD1DIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure BAUD1DIV at 133MHz target frequency.

Definition at line 625 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD1DIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure BAUD1DIV at 160MHz target frequency.

Definition at line 630 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD1DIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure BAUD1DIV at 200MHz target frequency.

Definition at line 635 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD1DIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure BAUD1DIV at 240MHz target frequency.

Definition at line 640 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD1DIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure BAUD1DIV at 300MHz target frequency.

Definition at line 645 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD1DIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure BAUD1DIV at 80MHz target frequency.

Definition at line 620 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD2DIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */

Macro to configure BAUD2DIV at 133MHz target frequency.

Definition at line 655 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD2DIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */

Macro to configure BAUD2DIV at 160MHz target frequency.

Definition at line 660 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD2DIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */

Macro to configure BAUD2DIV at 200MHz target frequency.

Definition at line 665 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD2DIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */

Macro to configure BAUD2DIV at 240MHz target frequency.

Definition at line 670 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD2DIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */

Macro to configure BAUD2DIV at 300MHz target frequency.

Definition at line 675 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD2DIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */

Macro to configure BAUD2DIV at 80MHz target frequency.

Definition at line 650 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BBBDIV_133MHZ   (IFXSCU_CFG_SRIDIV_133MHZ * 2)

Macro to configure BBBDIV at 133MHz target frequency.

Definition at line 985 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BBBDIV_160MHZ   (IFXSCU_CFG_SRIDIV_160MHZ * 2)

Macro to configure BBBDIV at 160MHz target frequency.

Definition at line 990 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BBBDIV_200MHZ   (IFXSCU_CFG_SRIDIV_200MHZ * 2)

Macro to configure BBBDIV at 200MHz target frequency.

Definition at line 995 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BBBDIV_240MHZ   (IFXSCU_CFG_SRIDIV_240MHZ * 2)

Macro to configure BBBDIV at 240MHz target frequency.

Definition at line 1000 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BBBDIV_300MHZ   (IFXSCU_CFG_SRIDIV_300MHZ * 2)

Macro to configure BBBDIV at 300MHz target frequency.

Definition at line 1005 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BBBDIV_80MHZ   (IFXSCU_CFG_SRIDIV_80MHZ * 2)

Macro to configure BBBDIV at 80MHz target frequency.

Definition at line 980 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CANDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure CANDIV at 133MHz target frequency.

Definition at line 775 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CANDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure CANDIV at 160MHz target frequency.

Definition at line 780 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CANDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure CANDIV at 200MHz target frequency.

Definition at line 785 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CANDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure CANDIV at 240MHz target frequency.

Definition at line 790 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CANDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure CANDIV at 200MHz target frequency.

Definition at line 795 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CANDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure CANDIV at 80MHz target frequency.

Definition at line 770 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON0   IFXSCU_CFG_CCUCON0_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1262 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON0_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON0_BASIC_(pllFreq)

Definition at line 1260 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON0_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_BAUD1DIV_##pllFreq << IFX_SCU_CCUCON0_BAUD1DIV_OFF) | \
(IFXSCU_CFG_BAUD2DIV_##pllFreq << IFX_SCU_CCUCON0_BAUD2DIV_OFF) | \
(IFXSCU_CFG_SRIDIV_##pllFreq << IFX_SCU_CCUCON0_SRIDIV_OFF) | \
(IFXSCU_CFG_SPBDIV_##pllFreq << IFX_SCU_CCUCON0_SPBDIV_OFF) | \
(IFXSCU_CFG_FSI2DIV_##pllFreq << IFX_SCU_CCUCON0_FSI2DIV_OFF) | \
(IFXSCU_CFG_FSIDIV_##pllFreq << IFX_SCU_CCUCON0_FSIDIV_OFF))

Definition at line 1251 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON0_MASK
Value:
( \
(IFX_SCU_CCUCON0_BAUD1DIV_MSK << IFX_SCU_CCUCON0_BAUD1DIV_OFF) | \
(IFX_SCU_CCUCON0_BAUD2DIV_MSK << IFX_SCU_CCUCON0_BAUD2DIV_OFF) | \
(IFX_SCU_CCUCON0_SRIDIV_MSK << IFX_SCU_CCUCON0_SRIDIV_OFF) | \
(IFX_SCU_CCUCON0_SPBDIV_MSK << IFX_SCU_CCUCON0_SPBDIV_OFF) | \
(IFX_SCU_CCUCON0_FSI2DIV_MSK << IFX_SCU_CCUCON0_FSI2DIV_OFF) | \
(IFX_SCU_CCUCON0_FSIDIV_MSK << IFX_SCU_CCUCON0_FSIDIV_OFF))

Macros to configure CCUCON0 Clock distribution.

Definition at line 1242 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON1   IFXSCU_CFG_CCUCON1_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1287 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON1_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON1_BASIC_(pllFreq)

Definition at line 1285 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON1_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_CANDIV_##pllFreq << IFX_SCU_CCUCON1_CANDIV_OFF) | \
(IFXSCU_CFG_ERAYDIV_80MHZ << IFX_SCU_CCUCON1_ERAYDIV_OFF) | \
(IFXSCU_CFG_STMDIV_##pllFreq << IFX_SCU_CCUCON1_STMDIV_OFF) | \
(IFXSCU_CFG_GTMDIV_##pllFreq << IFX_SCU_CCUCON1_GTMDIV_OFF) | \
(IFXSCU_CFG_ETHDIV_##pllFreq << IFX_SCU_CCUCON1_ETHDIV_OFF) | \
(IFXSCU_CFG_ASCLINFDIV_##pllFreq << IFX_SCU_CCUCON1_ASCLINFDIV_OFF) | \
(IFXSCU_CFG_ASCLINSDIV_##pllFreq << IFX_SCU_CCUCON1_ASCLINSDIV_OFF))

Definition at line 1275 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON1_MASK
Value:
( \
(IFX_SCU_CCUCON1_CANDIV_MSK << IFX_SCU_CCUCON1_CANDIV_OFF) | \
(IFX_SCU_CCUCON1_ERAYDIV_MSK << IFX_SCU_CCUCON1_ERAYDIV_OFF) | \
(IFX_SCU_CCUCON1_STMDIV_MSK << IFX_SCU_CCUCON1_STMDIV_OFF) | \
(IFX_SCU_CCUCON1_GTMDIV_MSK << IFX_SCU_CCUCON1_GTMDIV_OFF) | \
(IFX_SCU_CCUCON1_ETHDIV_MSK << IFX_SCU_CCUCON1_ETHDIV_OFF) | \
(IFX_SCU_CCUCON1_ASCLINFDIV_MSK << IFX_SCU_CCUCON1_ASCLINFDIV_OFF) | \
(IFX_SCU_CCUCON1_ASCLINSDIV_MSK << IFX_SCU_CCUCON1_ASCLINSDIV_OFF))

Macros to configure CCUCON1 Clock distribution.

Definition at line 1265 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON2   IFXSCU_CFG_CCUCON2_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1300 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON2_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON2_BASIC_(pllFreq)

Definition at line 1298 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON2_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_BBBDIV_##pllFreq << IFX_SCU_CCUCON2_BBBDIV_OFF))

Definition at line 1294 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON2_MASK
Value:
( \
(IFX_SCU_CCUCON2_BBBDIV_MSK << IFX_SCU_CCUCON2_BBBDIV_OFF))

Macros to configure CCUCON2 Clock distribution.

Definition at line 1290 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON5   IFXSCU_CFG_CCUCON5_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1313 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON5_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON5_BASIC_(pllFreq)

Definition at line 1311 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON5_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_MAXDIV_##pllFreq << IFX_SCU_CCUCON5_MAXDIV_OFF))

Definition at line 1307 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON5_MASK
Value:
( \
(IFX_SCU_CCUCON5_MAXDIV_MSK << IFX_SCU_CCUCON5_MAXDIV_OFF))

Macros to configure CCUCON5 Clock distribution.

Definition at line 1303 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON6   IFXSCU_CFG_CCUCON6_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1326 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON6_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON6_BASIC_(pllFreq)

Definition at line 1324 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON6_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_CPU0DIV_##pllFreq << IFX_SCU_CCUCON6_CPU0DIV_OFF))

Definition at line 1320 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON6_MASK
Value:
( \
(IFX_SCU_CCUCON6_CPU0DIV_MSK << IFX_SCU_CCUCON6_CPU0DIV_OFF))

Macros to configure CCUCON6 Clock distribution.

Definition at line 1316 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON7   IFXSCU_CFG_CCUCON7_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1339 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON7_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON7_BASIC_(pllFreq)

Definition at line 1337 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON7_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_CPU1DIV_##pllFreq << IFX_SCU_CCUCON7_CPU1DIV_OFF))

Definition at line 1333 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON7_MASK
Value:
( \
(IFX_SCU_CCUCON7_CPU1DIV_MSK << IFX_SCU_CCUCON7_CPU1DIV_OFF))

Macros to configure CCUCON7 Clock distribution.

Definition at line 1329 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON8   IFXSCU_CFG_CCUCON8_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1352 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON8_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON8_BASIC_(pllFreq)

Definition at line 1350 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON8_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_CPU2DIV_##pllFreq << IFX_SCU_CCUCON8_CPU2DIV_OFF))

Definition at line 1346 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON8_MASK
Value:
( \
(IFX_SCU_CCUCON8_CPU2DIV_MSK << IFX_SCU_CCUCON8_CPU2DIV_OFF))

Macros to configure CCUCON8 Clock distribution.

Definition at line 1342 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CLK_DISTRIBUTION
Value:
{ \
/* { uint32 value, uint32 mask }*/ \
{IFXSCU_CFG_CCUCON0, IFXSCU_CFG_CCUCON0_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon0;*/ \
{IFXSCU_CFG_CCUCON1, IFXSCU_CFG_CCUCON1_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon1;*/ \
{IFXSCU_CFG_CCUCON2, IFXSCU_CFG_CCUCON2_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon2;*/ \
{IFXSCU_CFG_CCUCON5, IFXSCU_CFG_CCUCON5_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon5;*/ \
{IFXSCU_CFG_CCUCON6, IFXSCU_CFG_CCUCON6_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon6;*/ \
{IFXSCU_CFG_CCUCON7, IFXSCU_CFG_CCUCON7_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon7;*/ \
{IFXSCU_CFG_CCUCON8, IFXSCU_CFG_CCUCON8_MASK} /*IfxScuCcu_CcuconRegConfig ccucon8;*/ \
}

Definition at line 1354 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU0DIV_133MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU0DIV at 133MHz target frequency.

Definition at line 1015 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU0DIV_160MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU0DIV at 160MHz target frequency.

Definition at line 1020 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU0DIV_200MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU0DIV at 200MHz target frequency.

Definition at line 1025 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU0DIV_240MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU0DIV at 240MHz target frequency.

Definition at line 1030 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU0DIV_300MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU0DIV at 300MHz target frequency.

Definition at line 1035 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU0DIV_80MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU0DIV at 80MHz target frequency.

Definition at line 1010 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU1DIV_133MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU1DIV at 133MHz target frequency.

Definition at line 1045 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU1DIV_160MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU1DIV at 160MHz target frequency.

Definition at line 1050 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU1DIV_200MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU1DIV at 200MHz target frequency.

Definition at line 1055 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU1DIV_240MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU1DIV at 240MHz target frequency.

Definition at line 1060 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU1DIV_300MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU1DIV at 300MHz target frequency.

Definition at line 1065 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU1DIV_80MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU1DIV at 80MHz target frequency.

Definition at line 1040 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU2DIV_133MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU2DIV at 133MHz target frequency.

Definition at line 1075 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU2DIV_160MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU2DIV at 160MHz target frequency.

Definition at line 1080 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU2DIV_200MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU2DIV at 200MHz target frequency.

Definition at line 1085 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU2DIV_240MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU2DIV at 240MHz target frequency.

Definition at line 1090 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU2DIV_300MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU2DIV at 300MHz target frequency.

Definition at line 1095 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU2DIV_80MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU2DIV at 80MHz target frequency.

Definition at line 1070 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ERAYDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 80MHz */

Macro to configure ERAYDIV at 133MHz target frequency.

Definition at line 805 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ERAYDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 80MHz */

Macro to configure ERAYDIV at 160MHz target frequency.

Definition at line 810 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ERAYDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 3) /*Max: 80MHz */

Macro to configure ERAYDIV at 200MHz target frequency.

Definition at line 815 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ERAYDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 80MHz */

Macro to configure ERAYDIV at 200MHz target frequency.

Definition at line 820 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ERAYDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 4) /*Max: 80MHz */

Macro to configure ERAYDIV at 300MHz target frequency.

Definition at line 825 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ERAYDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 80MHz */

Macro to configure ERAYDIV at 80MHz target frequency.

Definition at line 800 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ETHDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 3)

Macro to configure ETHDIV at 133MHz target frequency.

Definition at line 895 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ETHDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 4)

Macro to configure ETHDIV at 160MHz target frequency.

Definition at line 900 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ETHDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 4)

Macro to configure ETHDIV at 200MHz target frequency.

Definition at line 905 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ETHDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 5)

Macro to configure ETHDIV at 240MHz target frequency.

Definition at line 910 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ETHDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 6)

Macro to configure ETHDIV at 300MHz target frequency.

Definition at line 915 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ETHDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ * 2)

Macro to configure ETHDIV at 80MHz target frequency.

Definition at line 890 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_133MHZ   (14 - 1)

Macro to configure FCON.WSDFLASH_ at 133MHz target frequency, where fSRI= 133/2= 66.5MHZ.

Definition at line 1169 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_160MHZ   (16 - 1)

Macro to configure FCON.WSDFLASH at 160MHz target frequency, where fSRI= 160/2= 80MHZ.

Definition at line 1174 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_200MHZ   (20 - 1)

Macro to configure FCON.WSDFLASH at 200MHz target frequency, where fSRI= 200/2= 100MHZ.

Definition at line 1179 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_240MHZ   (16 - 1)

Macro to configure FCON.WSDFLASH at 240MHz target frequency, where fSRI= 240/3= 80MHZ.

Definition at line 1184 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_300MHZ   (20 - 1)

Macro to configure FCON.WSDFLASH at 300MHz target frequency, where fSRI= 300/3= 100MHZ.

Definition at line 1189 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_80MHZ   (16 - 1)

Macro to configure FCON.WSDFLASH at 80MHz target frequency.

Definition at line 1164 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECDF_133MHZ   (2 - 1)

Macro to configure FCON.WSECDF at 133MHz target frequency, where fSRI= 133/2= 66.5MHZ.

Definition at line 1199 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECDF_160MHZ   (2 - 1)

Macro to configure FCON.WSECDF at 160MHz target frequency, where fSRI= 160/2= 80MHZ.

Definition at line 1204 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECDF_200MHZ   (2 - 1)

Macro to configure FCON.WSECDF at 200MHz target frequency, where fSRI= 200/2= 100MHZ.

Definition at line 1209 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECDF_240MHZ   (2 - 1)

Macro to configure FCON.WSECDF at 240MHz target frequency, where fSRI= 240/3= 80MHZ.

Definition at line 1214 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECDF_300MHZ   (2 - 1)

Macro to configure FCON.WSECDF at 300MHz target frequency, where fSRI= 300/3= 100MHZ.

Definition at line 1219 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECDF_80MHZ   (2 - 1)

Macro to configure FCON.WSECDF at 80MHz target frequency.

Definition at line 1194 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECPF_133MHZ   (2 - 1)

Macro to configure FCON.WSECPF at 133MHz target frequency.

Definition at line 1139 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECPF_160MHZ   (2 - 1)

Macro to configure FCON.WSECPF at 160MHz target frequency.

Definition at line 1144 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECPF_200MHZ   (2 - 1)

Macro to configure FCON.WSECPF at 200MHz target frequency.

Definition at line 1149 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECPF_240MHZ   (3 - 1)

Macro to configure FCON.WSECPF_ at 240MHz target frequency.

Definition at line 1154 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECPF_300MHZ   (3 - 1)

Macro to configure FCON.WSECPF at 300MHz target frequency.

Definition at line 1159 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECPF_80MHZ   (1 - 1)

Macro to configure FCON.WSECP_ at 80MHz target frequency.

Definition at line 1134 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_133MHZ   (4 - 1)

Macro to configure FCON.WSPFLASH at 133MHz target frequency.

Definition at line 1109 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_160MHZ   (5 - 1)

Macro to configure FCON.WSPFLASH at 160MHz target frequency.

Definition at line 1114 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_200MHZ   (6 - 1)

Macro to configure FCON.WSPFLASH at 200MHz target frequency.

Definition at line 1119 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_240MHZ   (8 - 1)

Macro to configure FCON.WSPFLASH at 240MHz target frequency.

Definition at line 1124 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_300MHZ   (9 - 1)

Macro to configure FCON.WSPFLASH at 300MHz target frequency.

Definition at line 1129 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_80MHZ   (3 - 1)

Macros to configure FLASH.FCON register for flash waitstate configuration. IfxScu_InitialStepConfig.

Macro to configure FCON.WSPFLASH at 80MHz target frequency

Definition at line 1104 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_WAITSTATE
Value:
/* { uint32 value, uint32 mask }*/\
{IFXSCU_CFG_FLASH_WAITSTATE_VAL, IFXSCU_CFG_FLASH_WAITSTATE_MSK}

Definition at line 1377 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_WAITSTATE_MSK
Value:
( \
(IFX_FLASH_FCON_WSPFLASH_MSK << IFX_FLASH_FCON_WSPFLASH_OFF) | \
(IFX_FLASH_FCON_WSECPF_MSK << IFX_FLASH_FCON_WSECPF_OFF) | \
(IFX_FLASH_FCON_WSDFLASH_MSK << IFX_FLASH_FCON_WSDFLASH_OFF) | \
(IFX_FLASH_FCON_WSECDF_MSK << IFX_FLASH_FCON_WSECDF_OFF))

Macros to configure FLASH.FCON registers.

Definition at line 1223 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_WAITSTATE_VAL   IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1239 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC (   pllFreq)    IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_(pllFreq)

Definition at line 1237 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_ (   pllFreq)
Value:
( \
(IFXSCU_CFG_FLASH_FCON_WSPFLASH_##pllFreq << IFX_FLASH_FCON_WSPFLASH_OFF) | \
(IFXSCU_CFG_FLASH_FCON_WSECPF_##pllFreq << IFX_FLASH_FCON_WSECPF_OFF) | \
(IFXSCU_CFG_FLASH_FCON_WSDFLASH_##pllFreq << IFX_FLASH_FCON_WSDFLASH_OFF) | \
(IFXSCU_CFG_FLASH_FCON_WSECDF_##pllFreq << IFX_FLASH_FCON_WSECDF_OFF))

Definition at line 1230 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSI2DIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */

Macro to configure FSI2DIV at 133MHz target frequency.

Definition at line 715 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSI2DIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */

Macro to configure FSI2DIV at 160MHz target frequency.

Definition at line 720 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSI2DIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */

Macro to configure FSI2DIV at 200MHz target frequency.

Definition at line 725 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSI2DIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */

Macro to configure FSI2DIV at 240MHz target frequency.

Definition at line 730 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSI2DIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */

Macro to configure FSI2DIV at 300MHz target frequency.

Definition at line 735 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSI2DIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */

Macro to configure FSI2DIV at 80MHz target frequency.

Definition at line 710 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSIDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure FSIDIV at 133MHz target frequency.

Definition at line 745 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSIDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure FSIDIV at 160MHz target frequency.

Definition at line 750 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSIDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure FSIDIV at 200MHz target frequency.

Definition at line 755 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSIDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure FSIDIV at 240MHz target frequency.

Definition at line 760 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSIDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure FSIDIV at 300MHz target frequency.

Definition at line 765 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSIDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure FSIDIV at 80MHz target frequency.

Definition at line 740 of file IfxScu_cfg.h.

#define IFXSCU_CFG_GTMDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure GTMDIV at 133MHz target frequency.

Definition at line 865 of file IfxScu_cfg.h.

#define IFXSCU_CFG_GTMDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure GTMDIV at 160MHz target frequency.

Definition at line 870 of file IfxScu_cfg.h.

#define IFXSCU_CFG_GTMDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure GTMDIV at 200MHz target frequency.

Definition at line 875 of file IfxScu_cfg.h.

#define IFXSCU_CFG_GTMDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure GTMDIV at 240MHz target frequency.

Definition at line 880 of file IfxScu_cfg.h.

#define IFXSCU_CFG_GTMDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure GTMDIV at 300MHz target frequency.

Definition at line 885 of file IfxScu_cfg.h.

#define IFXSCU_CFG_GTMDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure GTMDIV at 80MHz target frequency.

Definition at line 860 of file IfxScu_cfg.h.

#define IFXSCU_CFG_MAXDIV_133MHZ   (1)

Macro to configure MAXDIV at 133MHz target frequency.

Definition at line 565 of file IfxScu_cfg.h.

#define IFXSCU_CFG_MAXDIV_160MHZ   (1)

Macro to configure MAXDIV at 160MHz target frequency.

Definition at line 570 of file IfxScu_cfg.h.

#define IFXSCU_CFG_MAXDIV_200MHZ   (1)

Macro to configure MAXDIV at 200MHz target frequency.

Definition at line 575 of file IfxScu_cfg.h.

#define IFXSCU_CFG_MAXDIV_240MHZ   (1)

Macro to configure MAXDIV at 240MHz target frequency.

Definition at line 580 of file IfxScu_cfg.h.

#define IFXSCU_CFG_MAXDIV_300MHZ   (1)

Macro to configure MAXDIV at 300MHz target frequency.

Definition at line 585 of file IfxScu_cfg.h.

#define IFXSCU_CFG_MAXDIV_80MHZ   (1)

Macros to configure CCUCON registers. Macros to configure the Pll initial step, where the configuration of PDIV, NDIV and K2DIV are done for the internal Oscillator frequency. IfxScu_InitialStepConfig.

Macros to configure CCUCON registers Macro to configure MAXDIV at 80MHz target frequency

Definition at line 560 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_FREQ   200MHZ

Definition at line 1401 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP   IFXSCU_CFG_PLL_INITIAL_STEP_BASIC(IFXSCU_CFG_XTAL_FREQ, IFXSCU_CFG_PLL_FREQ)

Definition at line 1375 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_133MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(1 - 1), (50 - 1), (8 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 16MHz Crystal and 133MHz target.

Definition at line 413 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_160MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(1 - 1), (40 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 16MHz Crystal and 160MHz target.

Definition at line 420 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_200MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(1 - 1), (50 - 1), (8 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 16MHz Crystal and 200MHz target.

Definition at line 427 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_240MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(1 - 1), (45 - 1), (7 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 16MHz Crystal and 240MHz target.

Definition at line 434 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_80MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(1 - 1), (40 - 1), (7 - 1), 0.000200F}

Macros to configure Initial Pll step. Macros to configure the Pll initial step, where the configuration of PDIV, NDIV and K2DIV are done for the internal Oscillator frequency. IfxScu_InitialStepConfig.

Macro for Initial Pll step, for profile with 16MHz Crystal and 80MHz target

Definition at line 406 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_133MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(2 - 1), (80 - 1), (8 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 20MHz Crystal and 133MHz target.

Definition at line 450 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_160MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(2 - 1), (64 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 20MHz Crystal and 160MHz target.

Definition at line 457 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_200MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(2 - 1), (60 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 20MHz Crystal and 200MHz target.

Definition at line 464 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_240MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(2 - 1), (72 - 1), (7 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 20MHz Crystal and 240MHz target.

Definition at line 471 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_300MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(2 - 1), (60 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 20MHz Crystal and 300MHz target.

Definition at line 478 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_80MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(2 - 1), (64 - 1), (7 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 20MHz Crystal and 80MHz target.

Definition at line 443 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_133MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(4 - 1), (80 - 1), (8 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 40MHz Crystal and 133MHz target.

Definition at line 494 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_160MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(4 - 1), (64 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 40MHz Crystal and 160MHz target.

Definition at line 501 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_200MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(4 - 1), (60 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 40MHz Crystal and 200MHz target.

Definition at line 508 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_240MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(4 - 1), (72 - 1), (7 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 40MHz Crystal and 240MHz target.

Definition at line 515 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_300MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(4 - 1), (60 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 40MHz Crystal and 300MHz target.

Definition at line 522 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_80MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(4 - 1), (64 - 1), (7 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 40MHz Crystal and 80MHz target.

Definition at line 487 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_160MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(1 - 1), (60 - 1), (5 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 8MHz Crystal and 160MHz target.

Definition at line 538 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_200MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
{(1 - 1), (75 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 8MHz Crystal and 200MHz target.

Definition at line 545 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_80MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime } ??*/\
{(1 - 1), (50 - 1), (5 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 8MHz Crystal and 80MHz target.

Definition at line 531 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC (   xtalFreq,
  pllFreq 
)    IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_(xtalFreq, pllFreq)

Definition at line 1374 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_ (   xtalFreq,
  pllFreq 
)    IFXSCU_CFG_PLL_INITIAL_STEP_##xtalFreq##_##pllFreq

Definition at line 1373 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS   IFXSCU_CFG_PLL_STEPS_BASIC(IFXSCU_CFG_XTAL_FREQ, IFXSCU_CFG_PLL_FREQ)

Definition at line 1370 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_16MHZ_133MHZ
Value:
{ /*Step 0 Config: 114MHz*/ \
(7 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 133MHz*/ \
(6 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 16MHz Crystal and 133MHz target.

Definition at line 80 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_16MHZ_160MHZ
Value:
{ /*Step 1 Config: 128MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 160MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 16MHz Crystal and 160MHz target.

Definition at line 95 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_16MHZ_200MHZ
Value:
{ /*Step 0 Config: 120MHz*/ \
(6 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 150MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 200MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 16MHz Crystal and 200MHz target.

Definition at line 110 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_16MHZ_240MHZ
Value:
{ /*Step 0 Config: 144MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 180MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 240MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 16MHz Crystal and 240MHz target.

Definition at line 130 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_16MHZ_80MHZ
Value:
{ /*Step 0 Config: 80MHz*/ \
(8 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macros to configure Pll steps, Macros to configure the Pll steps for different profiles of Crystal frequency and target frequencies. This configuration is important for the current jump controll during clock throttling. IfxScu_PllStepsConfig.

Macro for Pll step for profile with 16MHz Crystal and 80MHz target

Definition at line 70 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_20MHZ_133MHZ
Value:
{ /*Step 0 Config: 114MHz*/ \
(7 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 133MHz*/ \
(6 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 20MHz Crystal and 133MHz target.

Definition at line 161 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_20MHZ_160MHZ
Value:
{ /*Step 1 Config: 128MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 160MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 20MHz Crystal and 160MHz target.

Definition at line 176 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_20MHZ_200MHZ
Value:
{ /*Step 0 Config: 120MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 150MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 200MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 20MHz Crystal and 200MHz target.

Definition at line 191 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_20MHZ_240MHZ
Value:
{ /*Step 0 Config: 144MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 180MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 240MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 20MHz Crystal and 240MHz target.

Definition at line 211 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_20MHZ_300MHZ
Value:
{ /*Step 0 Config: 150MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 200MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 300MHz*/ \
(2 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 20MHz Crystal and 300MHz target.

Definition at line 231 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_20MHZ_80MHZ
Value:
{ /*Step 0 Config: 80MHz*/ \
(8 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 20MHz Crystal and 80MHz target.

Definition at line 151 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_40MHZ_133MHZ
Value:
{ /*Step 0 Config: 114MHz*/ \
(7 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 133MHz*/ \
(6 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 40MHz Crystal and 133MHz target.

Definition at line 262 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_40MHZ_160MHZ
Value:
{ /*Step 1 Config: 128MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 160MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 40MHz Crystal and 160MHz target.

Definition at line 277 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_40MHZ_200MHZ
Value:
{ /*Step 0 Config: 120MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 150MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 200MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 40MHz Crystal and 200MHz target.

Definition at line 292 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_40MHZ_240MHZ
Value:
{ /*Step 0 Config: 144MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 180MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 240MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 40MHz Crystal and 240MHz target.

Definition at line 312 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_40MHZ_300MHZ
Value:
{ /*Step 0 Config: 150MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 200MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 300MHz*/ \
(2 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 40MHz Crystal and 300MHz target.

Definition at line 332 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_40MHZ_80MHZ
Value:
{ /*Step 0 Config: 80MHz*/ \
(8 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 40MHz Crystal and 80MHz target.

Definition at line 252 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_8MHZ_160MHZ
Value:
{ /*Step 0 Config: 100MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 160MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 8MHz Crystal and 160MHz target.

Definition at line 363 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_8MHZ_200MHZ
Value:
{ /*Step 0 Config: 120MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 0 Config: 150MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 200MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 8MHz Crystal and 200MHz target.

Definition at line 378 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_8MHZ_80MHZ
Value:
{ /*Step 0 Config: 80MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 8MHz Crystal and 80MHz target.

Definition at line 353 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_BASIC (   xtalFreq,
  pllFreq 
)    IFXSCU_CFG_PLL_STEPS_BASIC_(xtalFreq, pllFreq)

Definition at line 1369 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_BASIC_ (   xtalFreq,
  pllFreq 
)    IFXSCU_CFG_PLL_STEPS_##xtalFreq##_##pllFreq

Definition at line 1368 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SPBDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure SPBDIV at 133MHz target frequency.

Definition at line 685 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SPBDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure SPBDIV at 160MHz target frequency.

Definition at line 690 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SPBDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure SPBDIV at 200MHz target frequency.

Definition at line 695 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SPBDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure SPBDIV at 240MHz target frequency.

Definition at line 700 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SPBDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure SPBDIV at 300MHz target frequency.

Definition at line 705 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SPBDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ * 2) /*Max: 100MHz */

Macro to configure SPBDIV at 80MHz target frequency.

Definition at line 680 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SRIDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */

Macro to configure SRIDIV at 133MHz target frequency.

Definition at line 595 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SRIDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */

Macro to configure SRIDIV at 160MHz target frequency.

Definition at line 600 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SRIDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */

Macro to configure SRIDIV at 200MHz target frequency.

Definition at line 605 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SRIDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */

Macro to configure SRIDIV at 240MHz target frequency.

Definition at line 610 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SRIDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */

Macro to configure SRIDIV at 300MHz target frequency.

Definition at line 615 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SRIDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */

Macro to configure SRIDIV at 80MHz target frequency.

Definition at line 590 of file IfxScu_cfg.h.

#define IFXSCU_CFG_STMDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure STMDIV at 133MHz target frequency.

Definition at line 835 of file IfxScu_cfg.h.

#define IFXSCU_CFG_STMDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure STMDIV at 160MHz target frequency.

Definition at line 840 of file IfxScu_cfg.h.

#define IFXSCU_CFG_STMDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure STMDIV at 200MHz target frequency.

Definition at line 845 of file IfxScu_cfg.h.

#define IFXSCU_CFG_STMDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure STMDIV at 240MHz target frequency.

Definition at line 850 of file IfxScu_cfg.h.

#define IFXSCU_CFG_STMDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure STMDIV at 300MHz target frequency.

Definition at line 855 of file IfxScu_cfg.h.

#define IFXSCU_CFG_STMDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure STMDIV at 80MHz target frequency.

Definition at line 830 of file IfxScu_cfg.h.

#define IFXSCU_CFG_XTAL_FREQ   20MHZ

Definition at line 1382 of file IfxScu_cfg.h.

#define IFXSCU_EVR_OSC_FREQUENCY   (100000000.0)

Definition at line 53 of file IfxScu_cfg.h.

Referenced by IfxScuCcu_getEvrFrequency(), and IfxScuCcu_getOscFrequency().

#define IFXSCU_PLL_FREERUNNING_FREQUENCY   (100000000.0)

Definition at line 57 of file IfxScu_cfg.h.

#define IFXSCU_VCO_BASE_FREQUENCY   (100000000.0)

Definition at line 52 of file IfxScu_cfg.h.

Referenced by IfxScuCcu_getPllErayFrequency(), IfxScuCcu_getPllErayVcoFrequency(), IfxScuCcu_getPllFrequency(), and IfxScuCcu_getPllVcoFrequency().

Enumeration Type Documentation

enum IfxScu_CCUCON0_CLKSEL

Clock selection

Enumerator
IfxScu_CCUCON0_CLKSEL_fBack 
IfxScu_CCUCON0_CLKSEL_fPll 

Definition at line 1411 of file IfxScu_cfg.h.

enum IfxScu_CCUCON1_INSEL

Input selection for PLL and PLL ERAY

Enumerator
IfxScu_CCUCON1_INSEL_fOsc1 
IfxScu_CCUCON1_INSEL_fOsc0 

Definition at line 1418 of file IfxScu_cfg.h.

enum IfxScu_PMCSR_REQSLP
Enumerator
IfxScu_PMCSR_REQSLP_Run 
IfxScu_PMCSR_REQSLP_Idle 
IfxScu_PMCSR_REQSLP_Sleep 
IfxScu_PMCSR_REQSLP_Stby 

Definition at line 1432 of file IfxScu_cfg.h.

enum IfxScu_WDTCON1_IR

Input frequency request control

Enumerator
IfxScu_WDTCON1_IR_divBy16384 
IfxScu_WDTCON1_IR_divBy256 
IfxScu_WDTCON1_IR_divBy64 

Definition at line 1425 of file IfxScu_cfg.h.