iLLD_TC27xD  1.0
IfxScu_cfg.h
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1 /**
2  * \file IfxScu_cfg.h
3  * \brief SCU on-chip implementation data
4  * \ingroup IfxLld_Scu
5  *
6  * \version iLLD_1_0_0_11_0
7  * \copyright Copyright (c) 2012 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Scu SCU
25  * \ingroup IfxLld
26  * \defgroup IfxLld_Scu_Impl Implementation
27  * \ingroup IfxLld_Scu
28  * \defgroup IfxLld_Scu_Std Standard Driver
29  * \ingroup IfxLld_Scu
30  */
31 
32 #ifndef IFXSCU_CFG_H
33 #define IFXSCU_CFG_H
34 /******************************************************************************/
35 #include "Ifx_Cfg.h"
36 #include "IfxScu_bf.h"
37 #include "IfxFlash_bf.h"
38 
39 /******************************************************************************/
40 /* Macro */
41 /******************************************************************************/
42 #ifndef IFX_CFG_SCU_XTAL_FREQUENCY
43 # define IFX_CFG_SCU_XTAL_FREQUENCY 20000000 /**< \brief Default External oscillator frequency */
44 # warning "IFX_CFG_SCU_XTAL_FREQUENCY not specified in your IfxCfg.h file."
45 # warning "Please doublecheck the external XTAL frequency with the default setting of 20 MHz!"
46 #endif
47 
48 #ifndef IFX_CFG_SCU_PLL_FREQUENCY
49 # define IFX_CFG_SCU_PLL_FREQUENCY 200000000 /**< \brief Default PLL frequency */
50 #endif
51 
52 #define IFXSCU_VCO_BASE_FREQUENCY (100000000.0)
53 #define IFXSCU_EVR_OSC_FREQUENCY (100000000.0)
54 
55 /*The following frequency is the PLL free running frequency */
56 /* FIXME is this not redundant to IFXSCU_VCO_BASE_FREQUENCY */
57 #define IFXSCU_PLL_FREERUNNING_FREQUENCY (100000000.0)
58 
59 /******************************************************************************/
60 /** \brief Macros to configure Pll steps,
61  * Macros to configure the Pll steps for different profiles of Crystal frequency and
62  * target frequencies. This configuration is important for the current jump controll
63  * during clock throttling.
64  * \ref IfxScu_PllStepsConfig
65  */
66 
67 /******************** Pll step for 16MHz crystal Configurations ********************************/
68 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_80MHZ
69 /** \brief Macro for Pll step for profile with 16MHz Crystal and 80MHz target */
70 #define IFXSCU_CFG_PLL_STEPS_16MHZ_80MHZ \
71  { /*Step 0 Config: 80MHz*/ \
72  (8 - 1), /*uint8 k2Step;*/ \
73  0.000100, /*float32 waitTime;*/ \
74  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
75  },
76 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_80MHZ */
77 
78 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_133MHZ
79 /** \brief Macro for Pll step for profile with 16MHz Crystal and 133MHz target */
80 #define IFXSCU_CFG_PLL_STEPS_16MHZ_133MHZ \
81  { /*Step 0 Config: 114MHz*/ \
82  (7 - 1), /*uint8 k2Step;*/ \
83  0.000100, /*float32 waitTime;*/ \
84  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
85  }, \
86  { /*Step 1 Config: 133MHz*/ \
87  (6 - 1), /*uint8 k2Step;*/ \
88  0.000100, /*float32 waitTime;*/ \
89  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
90  },
91 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_133MHZ */
92 
93 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_160MHZ
94 /** \brief Macro for Pll step for profile with 16MHz Crystal and 160MHz target */
95 #define IFXSCU_CFG_PLL_STEPS_16MHZ_160MHZ \
96  { /*Step 1 Config: 128MHz*/ \
97  (5 - 1), /*uint8 k2Step;*/ \
98  0.000100, /*float32 waitTime;*/ \
99  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
100  }, \
101  { /*Step 2 Config: 160MHz*/ \
102  (4 - 1), /*uint8 k2Step;*/ \
103  0.000100, /*float32 waitTime;*/ \
104  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
105  }
106 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_160MHZ */
107 
108 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_200MHZ
109 /** \brief Macro for Pll step for profile with 16MHz Crystal and 200MHz target */
110 #define IFXSCU_CFG_PLL_STEPS_16MHZ_200MHZ \
111  { /*Step 0 Config: 120MHz*/ \
112  (6 - 1), /*uint8 k2Step;*/ \
113  0.000100, /*float32 waitTime;*/ \
114  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
115  }, \
116  { /*Step 1 Config: 150MHz*/ \
117  (5 - 1), /*uint8 k2Step;*/ \
118  0.000100, /*float32 waitTime;*/ \
119  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
120  }, \
121  { /*Step 2 Config: 200MHz*/ \
122  (4 - 1), /*uint8 k2Step;*/ \
123  0.000100, /*float32 waitTime;*/ \
124  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
125  }
126 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_200MHZ */
127 
128 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_240MHZ
129 /** \brief Macro for Pll step for profile with 16MHz Crystal and 240MHz target */
130 #define IFXSCU_CFG_PLL_STEPS_16MHZ_240MHZ \
131  { /*Step 0 Config: 144MHz*/ \
132  (5 - 1), /*uint8 k2Step;*/ \
133  0.000100, /*float32 waitTime;*/ \
134  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
135  }, \
136  { /*Step 1 Config: 180MHz*/ \
137  (4 - 1), /*uint8 k2Step;*/ \
138  0.000100, /*float32 waitTime;*/ \
139  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
140  }, \
141  { /*Step 2 Config: 240MHz*/ \
142  (3 - 1), /*uint8 k2Step;*/ \
143  0.000100, /*float32 waitTime;*/ \
144  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
145  }
146 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_240MHZ */
147 
148 /******************** Pll step 20MHz crystal Configurations ********************************/
149 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_80MHZ
150 /** \brief Macro for Pll step for profile with 20MHz Crystal and 80MHz target */
151 #define IFXSCU_CFG_PLL_STEPS_20MHZ_80MHZ \
152  { /*Step 0 Config: 80MHz*/ \
153  (8 - 1), /*uint8 k2Step;*/ \
154  0.000100, /*float32 waitTime;*/ \
155  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
156  },
157 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_80MHZ */
158 
159 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_133MHZ
160 /** \brief Macro for Pll step for profile with 20MHz Crystal and 133MHz target */
161 #define IFXSCU_CFG_PLL_STEPS_20MHZ_133MHZ \
162  { /*Step 0 Config: 114MHz*/ \
163  (7 - 1), /*uint8 k2Step;*/ \
164  0.000100, /*float32 waitTime;*/ \
165  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
166  }, \
167  { /*Step 1 Config: 133MHz*/ \
168  (6 - 1), /*uint8 k2Step;*/ \
169  0.000100, /*float32 waitTime;*/ \
170  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
171  },
172 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_133MHZ */
173 
174 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_160MHZ
175 /** \brief Macro for Pll step for profile with 20MHz Crystal and 160MHz target */
176 #define IFXSCU_CFG_PLL_STEPS_20MHZ_160MHZ \
177  { /*Step 1 Config: 128MHz*/ \
178  (5 - 1), /*uint8 k2Step;*/ \
179  0.000100, /*float32 waitTime;*/ \
180  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
181  }, \
182  { /*Step 2 Config: 160MHz*/ \
183  (4 - 1), /*uint8 k2Step;*/ \
184  0.000100, /*float32 waitTime;*/ \
185  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
186  }
187 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_160MHZ */
188 
189 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_200MHZ
190 /** \brief Macro for Pll step for profile with 20MHz Crystal and 200MHz target */
191 #define IFXSCU_CFG_PLL_STEPS_20MHZ_200MHZ \
192  { /*Step 0 Config: 120MHz*/ \
193  (5 - 1), /*uint8 k2Step;*/ \
194  0.000100, /*float32 waitTime;*/ \
195  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
196  }, \
197  { /*Step 1 Config: 150MHz*/ \
198  (4 - 1), /*uint8 k2Step;*/ \
199  0.000100, /*float32 waitTime;*/ \
200  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
201  }, \
202  { /*Step 2 Config: 200MHz*/ \
203  (3 - 1), /*uint8 k2Step;*/ \
204  0.000100, /*float32 waitTime;*/ \
205  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
206  }
207 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_200MHZ */
208 
209 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_240MHZ
210 /** \brief Macro for Pll step for profile with 20MHz Crystal and 240MHz target */
211 #define IFXSCU_CFG_PLL_STEPS_20MHZ_240MHZ \
212  { /*Step 0 Config: 144MHz*/ \
213  (5 - 1), /*uint8 k2Step;*/ \
214  0.000100, /*float32 waitTime;*/ \
215  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
216  }, \
217  { /*Step 1 Config: 180MHz*/ \
218  (4 - 1), /*uint8 k2Step;*/ \
219  0.000100, /*float32 waitTime;*/ \
220  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
221  }, \
222  { /*Step 2 Config: 240MHz*/ \
223  (3 - 1), /*uint8 k2Step;*/ \
224  0.000100, /*float32 waitTime;*/ \
225  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
226  }
227 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_240MHZ */
228 
229 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_300MHZ
230 /** \brief Macro for Pll step for profile with 20MHz Crystal and 300MHz target */
231 #define IFXSCU_CFG_PLL_STEPS_20MHZ_300MHZ \
232  { /*Step 0 Config: 150MHz*/ \
233  (4 - 1), /*uint8 k2Step;*/ \
234  0.000100, /*float32 waitTime;*/ \
235  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
236  }, \
237  { /*Step 1 Config: 200MHz*/ \
238  (3 - 1), /*uint8 k2Step;*/ \
239  0.000100, /*float32 waitTime;*/ \
240  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
241  }, \
242  { /*Step 2 Config: 300MHz*/ \
243  (2 - 1), /*uint8 k2Step;*/ \
244  0.000100, /*float32 waitTime;*/ \
245  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
246  }
247 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_300MHZ */
248 
249 /******************** Pll step for 40MHz crystal Configurations ********************************/
250 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_80MHZ
251 /** \brief Macro for Pll step for profile with 40MHz Crystal and 80MHz target */
252 #define IFXSCU_CFG_PLL_STEPS_40MHZ_80MHZ \
253  { /*Step 0 Config: 80MHz*/ \
254  (8 - 1), /*uint8 k2Step;*/ \
255  0.000100, /*float32 waitTime;*/ \
256  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
257  },
258 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_80MHZ */
259 
260 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_133MHZ
261 /** \brief Macro for Pll step for profile with 40MHz Crystal and 133MHz target */
262 #define IFXSCU_CFG_PLL_STEPS_40MHZ_133MHZ \
263  { /*Step 0 Config: 114MHz*/ \
264  (7 - 1), /*uint8 k2Step;*/ \
265  0.000100, /*float32 waitTime;*/ \
266  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
267  }, \
268  { /*Step 1 Config: 133MHz*/ \
269  (6 - 1), /*uint8 k2Step;*/ \
270  0.000100, /*float32 waitTime;*/ \
271  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
272  },
273 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_133MHZ */
274 
275 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_160MHZ
276 /** \brief Macro for Pll step for profile with 40MHz Crystal and 160MHz target */
277 #define IFXSCU_CFG_PLL_STEPS_40MHZ_160MHZ \
278  { /*Step 1 Config: 128MHz*/ \
279  (5 - 1), /*uint8 k2Step;*/ \
280  0.000100, /*float32 waitTime;*/ \
281  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
282  }, \
283  { /*Step 2 Config: 160MHz*/ \
284  (4 - 1), /*uint8 k2Step;*/ \
285  0.000100, /*float32 waitTime;*/ \
286  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
287  }
288 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_160MHZ */
289 
290 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_200MHZ
291 /** \brief Macro for Pll step for profile with 40MHz Crystal and 200MHz target */
292 #define IFXSCU_CFG_PLL_STEPS_40MHZ_200MHZ \
293  { /*Step 0 Config: 120MHz*/ \
294  (5 - 1), /*uint8 k2Step;*/ \
295  0.000100, /*float32 waitTime;*/ \
296  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
297  }, \
298  { /*Step 1 Config: 150MHz*/ \
299  (4 - 1), /*uint8 k2Step;*/ \
300  0.000100, /*float32 waitTime;*/ \
301  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
302  }, \
303  { /*Step 2 Config: 200MHz*/ \
304  (3 - 1), /*uint8 k2Step;*/ \
305  0.000100, /*float32 waitTime;*/ \
306  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
307  }
308 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_200MHZ */
309 
310 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_240MHZ
311 /** \brief Macro for Pll step for profile with 40MHz Crystal and 240MHz target */
312 #define IFXSCU_CFG_PLL_STEPS_40MHZ_240MHZ \
313  { /*Step 0 Config: 144MHz*/ \
314  (5 - 1), /*uint8 k2Step;*/ \
315  0.000100, /*float32 waitTime;*/ \
316  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
317  }, \
318  { /*Step 1 Config: 180MHz*/ \
319  (4 - 1), /*uint8 k2Step;*/ \
320  0.000100, /*float32 waitTime;*/ \
321  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
322  }, \
323  { /*Step 2 Config: 240MHz*/ \
324  (3 - 1), /*uint8 k2Step;*/ \
325  0.000100, /*float32 waitTime;*/ \
326  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
327  }
328 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_240MHZ */
329 
330 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_300MHZ
331 /** \brief Macro for Pll step for profile with 40MHz Crystal and 300MHz target */
332 #define IFXSCU_CFG_PLL_STEPS_40MHZ_300MHZ \
333  { /*Step 0 Config: 150MHz*/ \
334  (4 - 1), /*uint8 k2Step;*/ \
335  0.000100, /*float32 waitTime;*/ \
336  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
337  }, \
338  { /*Step 1 Config: 200MHz*/ \
339  (3 - 1), /*uint8 k2Step;*/ \
340  0.000100, /*float32 waitTime;*/ \
341  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
342  }, \
343  { /*Step 2 Config: 300MHz*/ \
344  (2 - 1), /*uint8 k2Step;*/ \
345  0.000100, /*float32 waitTime;*/ \
346  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
347  }
348 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_300MHZ */
349 
350 /******************** Pll step for 8MHz crystal Configurations ********************************/
351 #ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_80MHZ
352 /** \brief Macro for Pll step for profile with 8MHz Crystal and 80MHz target */
353 #define IFXSCU_CFG_PLL_STEPS_8MHZ_80MHZ \
354  { /*Step 0 Config: 80MHz*/ \
355  (5 - 1), /*uint8 k2Step;*/ \
356  0.000100, /*float32 waitTime;*/ \
357  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
358  },
359 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_80MHZ */
360 
361 #ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_160MHZ
362 /** \brief Macro for Pll step for profile with 8MHz Crystal and 160MHz target */
363 #define IFXSCU_CFG_PLL_STEPS_8MHZ_160MHZ \
364  { /*Step 0 Config: 100MHz*/ \
365  (4 - 1), /*uint8 k2Step;*/ \
366  0.000100, /*float32 waitTime;*/ \
367  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
368  }, \
369  { /*Step 1 Config: 160MHz*/ \
370  (3 - 1), /*uint8 k2Step;*/ \
371  0.000100, /*float32 waitTime;*/ \
372  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
373  },
374 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_160MHZ */
375 
376 #ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_200MHZ
377 /** \brief Macro for Pll step for profile with 8MHz Crystal and 200MHz target */
378 #define IFXSCU_CFG_PLL_STEPS_8MHZ_200MHZ \
379  { /*Step 0 Config: 120MHz*/ \
380  (5 - 1), /*uint8 k2Step;*/ \
381  0.000100, /*float32 waitTime;*/ \
382  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
383  }, \
384  { /*Step 0 Config: 150MHz*/ \
385  (4 - 1), /*uint8 k2Step;*/ \
386  0.000100, /*float32 waitTime;*/ \
387  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
388  }, \
389  { /*Step 1 Config: 200MHz*/ \
390  (3 - 1), /*uint8 k2Step;*/ \
391  0.000100, /*float32 waitTime;*/ \
392  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
393  },
394 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_200MHZ */
395 
396 /** \brief Macros to configure Initial Pll step.
397  * Macros to configure the Pll initial step, where the configuration of PDIV, NDIV and K2DIV are
398  * done for the internal Oscillator frequency.
399  * \ref IfxScu_InitialStepConfig
400  */
401 
402 /****************** Initial Pll step for 16MHz crystal Configurations ******************************/
403 
404 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_80MHZ
405 /** \brief Macro for Initial Pll step, for profile with 16MHz Crystal and 80MHz target */
406 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_80MHZ \
407 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
408  {(1 - 1), (40 - 1), (7 - 1), 0.000200F}
409 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_80MHZ */
410 
411 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_133MHZ
412 /** \brief Macro for Initial Pll step, for profile with 16MHz Crystal and 133MHz target */
413 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_133MHZ \
414 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
415  {(1 - 1), (50 - 1), (8 - 1), 0.000200F}
416 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_133MHZ */
417 
418 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_160MHZ
419 /** \brief Macro for Initial Pll step, for profile with 16MHz Crystal and 160MHz target */
420 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_160MHZ \
421 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
422  {(1 - 1), (40 - 1), (6 - 1), 0.000200F}
423 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_160MHZ */
424 
425 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_200MHZ
426 /** \brief Macro for Initial Pll step, for profile with 16MHz Crystal and 200MHz target */
427 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_200MHZ \
428 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
429  {(1 - 1), (50 - 1), (8 - 1), 0.000200F}
430 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_200MHZ */
431 
432 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_240MHZ
433 /** \brief Macro for Initial Pll step, for profile with 16MHz Crystal and 240MHz target */
434 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_240MHZ \
435 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
436  {(1 - 1), (45 - 1), (7 - 1), 0.000200F}
437 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_240MHZ */
438 
439 /****************** Initial Pll step for 20MHz crystal Configurations ******************************/
440 
441 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_80MHZ
442 /** \brief Macro for Initial Pll step, for profile with 20MHz Crystal and 80MHz target */
443 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_80MHZ \
444 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
445  {(2 - 1), (64 - 1), (7 - 1), 0.000200F}
446 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_80MHZ */
447 
448 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_133MHZ
449 /** \brief Macro for Initial Pll step, for profile with 20MHz Crystal and 133MHz target */
450 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_133MHZ \
451 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
452  {(2 - 1), (80 - 1), (8 - 1), 0.000200F}
453 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_133MHZ */
454 
455 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_160MHZ
456 /** \brief Macro for Initial Pll step, for profile with 20MHz Crystal and 160MHz target */
457 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_160MHZ \
458 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
459  {(2 - 1), (64 - 1), (6 - 1), 0.000200F}
460 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_160MHZ */
461 
462 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_200MHZ
463 /** \brief Macro for Initial Pll step, for profile with 20MHz Crystal and 200MHz target */
464 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_200MHZ \
465 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
466  {(2 - 1), (60 - 1), (6 - 1), 0.000200F}
467 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_200MHZ */
468 
469 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_240MHZ
470 /** \brief Macro for Initial Pll step, for profile with 20MHz Crystal and 240MHz target */
471 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_240MHZ \
472 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
473  {(2 - 1), (72 - 1), (7 - 1), 0.000200F}
474 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_240MHZ */
475 
476 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_300MHZ
477 /** \brief Macro for Initial Pll step, for profile with 20MHz Crystal and 300MHz target */
478 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_300MHZ \
479 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
480  {(2 - 1), (60 - 1), (6 - 1), 0.000200F}
481 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_300MHZ */
482 
483 /****************** Initial Pll step for 40MHz crystal Configurations ******************************/
484 
485 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_80MHZ
486 /** \brief Macro for Initial Pll step, for profile with 40MHz Crystal and 80MHz target */
487 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_80MHZ \
488 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
489  {(4 - 1), (64 - 1), (7 - 1), 0.000200F}
490 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_80MHZ */
491 
492 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_133MHZ
493 /** \brief Macro for Initial Pll step, for profile with 40MHz Crystal and 133MHz target */
494 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_133MHZ \
495 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
496  {(4 - 1), (80 - 1), (8 - 1), 0.000200F}
497 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_133MHZ */
498 
499 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_160MHZ
500 /** \brief Macro for Initial Pll step, for profile with 40MHz Crystal and 160MHz target */
501 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_160MHZ \
502 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
503  {(4 - 1), (64 - 1), (6 - 1), 0.000200F}
504 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_160MHZ */
505 
506 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_200MHZ
507 /** \brief Macro for Initial Pll step, for profile with 40MHz Crystal and 200MHz target */
508 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_200MHZ \
509 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
510  {(4 - 1), (60 - 1), (6 - 1), 0.000200F}
511 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_200MHZ */
512 
513 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_240MHZ
514 /** \brief Macro for Initial Pll step, for profile with 40MHz Crystal and 240MHz target */
515 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_240MHZ \
516 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
517  {(4 - 1), (72 - 1), (7 - 1), 0.000200F}
518 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_240MHZ */
519 
520 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_300MHZ
521 /** \brief Macro for Initial Pll step, for profile with 40MHz Crystal and 300MHz target */
522 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_300MHZ \
523 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
524  {(4 - 1), (60 - 1), (6 - 1), 0.000200F}
525 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_300MHZ */
526 
527 /****************** Initial Pll step for 8MHz crystal Configurations ******************************/
528 
529 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_80MHZ
530 /** \brief Macro for Initial Pll step, for profile with 8MHz Crystal and 80MHz target */
531 #define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_80MHZ \
532 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime } ??*/\
533  {(1 - 1), (50 - 1), (5 - 1), 0.000200F}
534 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_80MHZ */
535 
536 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_160MHZ
537 /** \brief Macro for Initial Pll step, for profile with 8MHz Crystal and 160MHz target */
538 #define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_160MHZ \
539 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
540  {(1 - 1), (60 - 1), (5 - 1), 0.000200F}
541 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_160MHZ */
542 
543 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_200MHZ
544 /** \brief Macro for Initial Pll step, for profile with 8MHz Crystal and 200MHz target */
545 #define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_200MHZ \
546 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/\
547  {(1 - 1), (75 - 1), (6 - 1), 0.000200F}
548 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_200MHZ */
549 
550 /** \brief Macros to configure CCUCON registers.
551  * Macros to configure the Pll initial step, where the configuration of PDIV, NDIV and K2DIV are
552  * done for the internal Oscillator frequency.
553  * \ref IfxScu_InitialStepConfig
554  */
555 
556 /** \brief Macros to configure CCUCON registers */
557 
558 #ifndef IFXSCU_CFG_MAXDIV_80MHZ
559 /** \brief Macro to configure MAXDIV at 80MHz target frequency */
560 #define IFXSCU_CFG_MAXDIV_80MHZ (1)
561 #endif /*#ifndef IFXSCU_CFG_MAXDIV_80MHZ */
562 
563 #ifndef IFXSCU_CFG_MAXDIV_133MHZ
564 /** \brief Macro to configure MAXDIV at 133MHz target frequency */
565 #define IFXSCU_CFG_MAXDIV_133MHZ (1)
566 #endif /*#ifndef IFXSCU_CFG_MAXDIV_133MHZ */
567 
568 #ifndef IFXSCU_CFG_MAXDIV_160MHZ
569 /** \brief Macro to configure MAXDIV at 160MHz target frequency */
570 #define IFXSCU_CFG_MAXDIV_160MHZ (1)
571 #endif /*#ifndef IFXSCU_CFG_MAXDIV_160MHZ */
572 
573 #ifndef IFXSCU_CFG_MAXDIV_200MHZ
574 /** \brief Macro to configure MAXDIV at 200MHz target frequency */
575 #define IFXSCU_CFG_MAXDIV_200MHZ (1)
576 #endif /*#ifndef IFXSCU_CFG_MAXDIV_200MHZ */
577 
578 #ifndef IFXSCU_CFG_MAXDIV_240MHZ
579 /** \brief Macro to configure MAXDIV at 240MHz target frequency */
580 #define IFXSCU_CFG_MAXDIV_240MHZ (1)
581 #endif /*#ifndef IFXSCU_CFG_MAXDIV_240MHZ */
582 
583 #ifndef IFXSCU_CFG_MAXDIV_300MHZ
584 /** \brief Macro to configure MAXDIV at 300MHz target frequency */
585 #define IFXSCU_CFG_MAXDIV_300MHZ (1)
586 #endif /*#ifndef IFXSCU_CFG_MAXDIV_300MHZ */
587 
588 #ifndef IFXSCU_CFG_SRIDIV_80MHZ
589 /** \brief Macro to configure SRIDIV at 80MHz target frequency */
590 #define IFXSCU_CFG_SRIDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
591 #endif /*#ifndef IFXSCU_CFG_SRIDIV_80MHZ */
592 
593 #ifndef IFXSCU_CFG_SRIDIV_133MHZ
594 /** \brief Macro to configure SRIDIV at 133MHz target frequency */
595 #define IFXSCU_CFG_SRIDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
596 #endif /*#ifndef IFXSCU_CFG_SRIDIV_133MHZ */
597 
598 #ifndef IFXSCU_CFG_SRIDIV_160MHZ
599 /** \brief Macro to configure SRIDIV at 160MHz target frequency */
600 #define IFXSCU_CFG_SRIDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
601 #endif /*#ifndef IFXSCU_CFG_SRIDIV_160MHZ */
602 
603 #ifndef IFXSCU_CFG_SRIDIV_200MHZ
604 /** \brief Macro to configure SRIDIV at 200MHz target frequency */
605 #define IFXSCU_CFG_SRIDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
606 #endif /*#ifndef IFXSCU_CFG_SRIDIV_200MHZ */
607 
608 #ifndef IFXSCU_CFG_SRIDIV_240MHZ
609 /** \brief Macro to configure SRIDIV at 240MHz target frequency */
610 #define IFXSCU_CFG_SRIDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
611 #endif /*#ifndef IFXSCU_CFG_SRIDIV_240MHZ */
612 
613 #ifndef IFXSCU_CFG_SRIDIV_300MHZ
614 /** \brief Macro to configure SRIDIV at 300MHz target frequency */
615 #define IFXSCU_CFG_SRIDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
616 #endif /*#ifndef IFXSCU_CFG_SRIDIV_300MHZ */
617 
618 #ifndef IFXSCU_CFG_BAUD1DIV_80MHZ
619 /** \brief Macro to configure BAUD1DIV at 80MHz target frequency */
620 #define IFXSCU_CFG_BAUD1DIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
621 #endif /*#ifndef IFXSCU_CFG_BAUD1DIV_80MHZ */
622 
623 #ifndef IFXSCU_CFG_BAUD1DIV_133MHZ
624 /** \brief Macro to configure BAUD1DIV at 133MHz target frequency */
625 #define IFXSCU_CFG_BAUD1DIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
626 #endif /*#ifndef IFXSCU_CFG_BAUD1DIV_133MHZ */
627 
628 #ifndef IFXSCU_CFG_BAUD1DIV_160MHZ
629 /** \brief Macro to configure BAUD1DIV at 160MHz target frequency */
630 #define IFXSCU_CFG_BAUD1DIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
631 #endif /*#ifndef IFXSCU_CFG_BAUD1DIV_160MHZ */
632 
633 #ifndef IFXSCU_CFG_BAUD1DIV_200MHZ
634 /** \brief Macro to configure BAUD1DIV at 200MHz target frequency */
635 #define IFXSCU_CFG_BAUD1DIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
636 #endif /*#ifndef IFXSCU_CFG_BAUD1DIV_200MHZ */
637 
638 #ifndef IFXSCU_CFG_BAUD1DIV_240MHZ
639 /** \brief Macro to configure BAUD1DIV at 240MHz target frequency */
640 #define IFXSCU_CFG_BAUD1DIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
641 #endif /*#ifndef IFXSCU_CFG_BAUD1DIV_240MHZ */
642 
643 #ifndef IFXSCU_CFG_BAUD1DIV_300MHZ
644 /** \brief Macro to configure BAUD1DIV at 300MHz target frequency */
645 #define IFXSCU_CFG_BAUD1DIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
646 #endif /*#ifndef IFXSCU_CFG_BAUD1DIV_300MHZ */
647 
648 #ifndef IFXSCU_CFG_BAUD2DIV_80MHZ
649 /** \brief Macro to configure BAUD2DIV at 80MHz target frequency */
650 #define IFXSCU_CFG_BAUD2DIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
651 #endif /*#ifndef IFXSCU_CFG_BAUD2DIV_80MHZ */
652 
653 #ifndef IFXSCU_CFG_BAUD2DIV_133MHZ
654 /** \brief Macro to configure BAUD2DIV at 133MHz target frequency */
655 #define IFXSCU_CFG_BAUD2DIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
656 #endif /*#ifndef IFXSCU_CFG_BAUD2DIV_133MHZ */
657 
658 #ifndef IFXSCU_CFG_BAUD2DIV_160MHZ
659 /** \brief Macro to configure BAUD2DIV at 160MHz target frequency */
660 #define IFXSCU_CFG_BAUD2DIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
661 #endif /*#ifndef IFXSCU_CFG_BAUD2DIV_160MHZ */
662 
663 #ifndef IFXSCU_CFG_BAUD2DIV_200MHZ
664 /** \brief Macro to configure BAUD2DIV at 200MHz target frequency */
665 #define IFXSCU_CFG_BAUD2DIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
666 #endif /*#ifndef IFXSCU_CFG_BAUD2DIV_200MHZ */
667 
668 #ifndef IFXSCU_CFG_BAUD2DIV_240MHZ
669 /** \brief Macro to configure BAUD2DIV at 240MHz target frequency */
670 #define IFXSCU_CFG_BAUD2DIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
671 #endif /*#ifndef IFXSCU_CFG_BAUD2DIV_240MHZ */
672 
673 #ifndef IFXSCU_CFG_BAUD2DIV_300MHZ
674 /** \brief Macro to configure BAUD2DIV at 300MHz target frequency */
675 #define IFXSCU_CFG_BAUD2DIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
676 #endif /*#ifndef IFXSCU_CFG_BAUD2DIV_300MHZ */
677 
678 #ifndef IFXSCU_CFG_SPBDIV_80MHZ
679 /** \brief Macro to configure SPBDIV at 80MHz target frequency */
680 #define IFXSCU_CFG_SPBDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ * 2) /*Max: 100MHz */
681 #endif /*#ifndef IFXSCU_CFG_SPBDIV_80MHZ */
682 
683 #ifndef IFXSCU_CFG_SPBDIV_133MHZ
684 /** \brief Macro to configure SPBDIV at 133MHz target frequency */
685 #define IFXSCU_CFG_SPBDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
686 #endif /*#ifndef IFXSCU_CFG_SPBDIV_133MHZ */
687 
688 #ifndef IFXSCU_CFG_SPBDIV_160MHZ
689 /** \brief Macro to configure SPBDIV at 160MHz target frequency */
690 #define IFXSCU_CFG_SPBDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
691 #endif /*#ifndef IFXSCU_CFG_SPBDIV_160MHZ */
692 
693 #ifndef IFXSCU_CFG_SPBDIV_200MHZ
694 /** \brief Macro to configure SPBDIV at 200MHz target frequency */
695 #define IFXSCU_CFG_SPBDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
696 #endif /*#ifndef IFXSCU_CFG_SPBDIV_200MHZ */
697 
698 #ifndef IFXSCU_CFG_SPBDIV_240MHZ
699 /** \brief Macro to configure SPBDIV at 240MHz target frequency */
700 #define IFXSCU_CFG_SPBDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
701 #endif /*#ifndef IFXSCU_CFG_SPBDIV_240MHZ */
702 
703 #ifndef IFXSCU_CFG_SPBDIV_300MHZ
704 /** \brief Macro to configure SPBDIV at 300MHz target frequency */
705 #define IFXSCU_CFG_SPBDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
706 #endif /*#ifndef IFXSCU_CFG_SPBDIV_300MHZ */
707 
708 #ifndef IFXSCU_CFG_FSI2DIV_80MHZ
709 /** \brief Macro to configure FSI2DIV at 80MHz target frequency */
710 #define IFXSCU_CFG_FSI2DIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
711 #endif /*#ifndef IFXSCU_CFG_FSI2DIV_80MHZ */
712 
713 #ifndef IFXSCU_CFG_FSI2DIV_133MHZ
714 /** \brief Macro to configure FSI2DIV at 133MHz target frequency */
715 #define IFXSCU_CFG_FSI2DIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
716 #endif /*#ifndef IFXSCU_CFG_FSI2DIV_133MHZ */
717 
718 #ifndef IFXSCU_CFG_FSI2DIV_160MHZ
719 /** \brief Macro to configure FSI2DIV at 160MHz target frequency */
720 #define IFXSCU_CFG_FSI2DIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
721 #endif /*#ifndef IFXSCU_CFG_FSI2DIV_160MHZ */
722 
723 #ifndef IFXSCU_CFG_FSI2DIV_200MHZ
724 /** \brief Macro to configure FSI2DIV at 200MHz target frequency */
725 #define IFXSCU_CFG_FSI2DIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
726 #endif /*#ifndef IFXSCU_CFG_FSI2DIV_200MHZ */
727 
728 #ifndef IFXSCU_CFG_FSI2DIV_240MHZ
729 /** \brief Macro to configure FSI2DIV at 240MHz target frequency */
730 #define IFXSCU_CFG_FSI2DIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
731 #endif /*#ifndef IFXSCU_CFG_FSI2DIV_240MHZ */
732 
733 #ifndef IFXSCU_CFG_FSI2DIV_300MHZ
734 /** \brief Macro to configure FSI2DIV at 300MHz target frequency */
735 #define IFXSCU_CFG_FSI2DIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
736 #endif /*#ifndef IFXSCU_CFG_FSI2DIV_300MHZ */
737 
738 #ifndef IFXSCU_CFG_FSIDIV_80MHZ
739 /** \brief Macro to configure FSIDIV at 80MHz target frequency */
740 #define IFXSCU_CFG_FSIDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
741 #endif /*#ifndef IFXSCU_CFG_FSIDIV_80MHZ */
742 
743 #ifndef IFXSCU_CFG_FSIDIV_133MHZ
744 /** \brief Macro to configure FSIDIV at 133MHz target frequency */
745 #define IFXSCU_CFG_FSIDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
746 #endif /*#ifndef IFXSCU_CFG_FSIDIV_133MHZ */
747 
748 #ifndef IFXSCU_CFG_FSIDIV_160MHZ
749 /** \brief Macro to configure FSIDIV at 160MHz target frequency */
750 #define IFXSCU_CFG_FSIDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
751 #endif /*#ifndef IFXSCU_CFG_FSIDIV_160MHZ */
752 
753 #ifndef IFXSCU_CFG_FSIDIV_200MHZ
754 /** \brief Macro to configure FSIDIV at 200MHz target frequency */
755 #define IFXSCU_CFG_FSIDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
756 #endif /*#ifndef IFXSCU_CFG_FSIDIV_200MHZ */
757 
758 #ifndef IFXSCU_CFG_FSIDIV_240MHZ
759 /** \brief Macro to configure FSIDIV at 240MHz target frequency */
760 #define IFXSCU_CFG_FSIDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
761 #endif /*#ifndef IFXSCU_CFG_FSIDIV_240MHZ */
762 
763 #ifndef IFXSCU_CFG_FSIDIV_300MHZ
764 /** \brief Macro to configure FSIDIV at 300MHz target frequency */
765 #define IFXSCU_CFG_FSIDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
766 #endif /*#ifndef IFXSCU_CFG_FSIDIV_300MHZ */
767 
768 #ifndef IFXSCU_CFG_CANDIV_80MHZ
769 /** \brief Macro to configure CANDIV at 80MHz target frequency */
770 #define IFXSCU_CFG_CANDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
771 #endif /*#ifndef IFXSCU_CFG_CANDIV_80MHZ */
772 
773 #ifndef IFXSCU_CFG_CANDIV_133MHZ
774 /** \brief Macro to configure CANDIV at 133MHz target frequency */
775 #define IFXSCU_CFG_CANDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
776 #endif /*#ifndef IFXSCU_CFG_CANDIV_133MHZ */
777 
778 #ifndef IFXSCU_CFG_CANDIV_160MHZ
779 /** \brief Macro to configure CANDIV at 160MHz target frequency */
780 #define IFXSCU_CFG_CANDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
781 #endif /*#ifndef IFXSCU_CFG_CANDIV_160MHZ */
782 
783 #ifndef IFXSCU_CFG_CANDIV_200MHZ
784 /** \brief Macro to configure CANDIV at 200MHz target frequency */
785 #define IFXSCU_CFG_CANDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
786 #endif /*#ifndef IFXSCU_CFG_CANDIV_200MHZ */
787 
788 #ifndef IFXSCU_CFG_CANDIV_240MHZ
789 /** \brief Macro to configure CANDIV at 240MHz target frequency */
790 #define IFXSCU_CFG_CANDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
791 #endif /*#ifndef IFXSCU_CFG_CANDIV_240MHZ */
792 
793 #ifndef IFXSCU_CFG_CANDIV_300MHZ
794 /** \brief Macro to configure CANDIV at 200MHz target frequency */
795 #define IFXSCU_CFG_CANDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
796 #endif /*#ifndef IFXSCU_CFG_CANDIV_300MHZ */
797 
798 #ifndef IFXSCU_CFG_ERAYDIV_80MHZ
799 /** \brief Macro to configure ERAYDIV at 80MHz target frequency */
800 #define IFXSCU_CFG_ERAYDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 80MHz */
801 #endif /*#ifndef IFXSCU_CFG_ERAYDIV_80MHZ */
802 
803 #ifndef IFXSCU_CFG_ERAYDIV_133MHZ
804 /** \brief Macro to configure ERAYDIV at 133MHz target frequency */
805 #define IFXSCU_CFG_ERAYDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 80MHz */
806 #endif /*#ifndef IFXSCU_CFG_ERAYDIV_133MHZ */
807 
808 #ifndef IFXSCU_CFG_ERAYDIV_160MHZ
809 /** \brief Macro to configure ERAYDIV at 160MHz target frequency */
810 #define IFXSCU_CFG_ERAYDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 80MHz */
811 #endif /*#ifndef IFXSCU_CFG_ERAYDIV_160MHZ */
812 
813 #ifndef IFXSCU_CFG_ERAYDIV_200MHZ
814 /** \brief Macro to configure ERAYDIV at 200MHz target frequency */
815 #define IFXSCU_CFG_ERAYDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 3) /*Max: 80MHz */
816 #endif /*#ifndef IFXSCU_CFG_ERAYDIV_200MHZ */
817 
818 #ifndef IFXSCU_CFG_ERAYDIV_240MHZ
819 /** \brief Macro to configure ERAYDIV at 200MHz target frequency */
820 #define IFXSCU_CFG_ERAYDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 80MHz */
821 #endif /*#ifndef IFXSCU_CFG_ERAYDIV_240MHZ */
822 
823 #ifndef IFXSCU_CFG_ERAYDIV_300MHZ
824 /** \brief Macro to configure ERAYDIV at 300MHz target frequency */
825 #define IFXSCU_CFG_ERAYDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 4) /*Max: 80MHz */
826 #endif /*#ifndef IFXSCU_CFG_ERAYDIV_300MHZ */
827 
828 #ifndef IFXSCU_CFG_STMDIV_80MHZ
829 /** \brief Macro to configure STMDIV at 80MHz target frequency */
830 #define IFXSCU_CFG_STMDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
831 #endif /*#ifndef IFXSCU_CFG_STMDIV_80MHZ */
832 
833 #ifndef IFXSCU_CFG_STMDIV_133MHZ
834 /** \brief Macro to configure STMDIV at 133MHz target frequency */
835 #define IFXSCU_CFG_STMDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
836 #endif /*#ifndef IFXSCU_CFG_STMDIV_133MHZ */
837 
838 #ifndef IFXSCU_CFG_STMDIV_160MHZ
839 /** \brief Macro to configure STMDIV at 160MHz target frequency */
840 #define IFXSCU_CFG_STMDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
841 #endif /*#ifndef IFXSCU_CFG_STMDIV_160MHZ */
842 
843 #ifndef IFXSCU_CFG_STMDIV_200MHZ
844 /** \brief Macro to configure STMDIV at 200MHz target frequency */
845 #define IFXSCU_CFG_STMDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
846 #endif /*#ifndef IFXSCU_CFG_STMDIV_200MHZ */
847 
848 #ifndef IFXSCU_CFG_STMDIV_240MHZ
849 /** \brief Macro to configure STMDIV at 240MHz target frequency */
850 #define IFXSCU_CFG_STMDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
851 #endif /*#ifndef IFXSCU_CFG_STMDIV_240MHZ */
852 
853 #ifndef IFXSCU_CFG_STMDIV_300MHZ
854 /** \brief Macro to configure STMDIV at 300MHz target frequency */
855 #define IFXSCU_CFG_STMDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
856 #endif /*#ifndef IFXSCU_CFG_STMDIV_300MHZ */
857 
858 #ifndef IFXSCU_CFG_GTMDIV_80MHZ
859 /** \brief Macro to configure GTMDIV at 80MHz target frequency */
860 #define IFXSCU_CFG_GTMDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
861 #endif /*#ifndef IFXSCU_CFG_GTMDIV_80MHZ */
862 
863 #ifndef IFXSCU_CFG_GTMDIV_133MHZ
864 /** \brief Macro to configure GTMDIV at 133MHz target frequency */
865 #define IFXSCU_CFG_GTMDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
866 #endif /*#ifndef IFXSCU_CFG_GTMDIV_133MHZ */
867 
868 #ifndef IFXSCU_CFG_GTMDIV_160MHZ
869 /** \brief Macro to configure GTMDIV at 160MHz target frequency */
870 #define IFXSCU_CFG_GTMDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
871 #endif /*#ifndef IFXSCU_CFG_GTMDIV_160MHZ */
872 
873 #ifndef IFXSCU_CFG_GTMDIV_200MHZ
874 /** \brief Macro to configure GTMDIV at 200MHz target frequency */
875 #define IFXSCU_CFG_GTMDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
876 #endif /*#ifndef IFXSCU_CFG_GTMDIV_200MHZ */
877 
878 #ifndef IFXSCU_CFG_GTMDIV_240MHZ
879 /** \brief Macro to configure GTMDIV at 240MHz target frequency */
880 #define IFXSCU_CFG_GTMDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
881 #endif /*#ifndef IFXSCU_CFG_GTMDIV_240MHZ */
882 
883 #ifndef IFXSCU_CFG_GTMDIV_300MHZ
884 /** \brief Macro to configure GTMDIV at 300MHz target frequency */
885 #define IFXSCU_CFG_GTMDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
886 #endif /*#ifndef IFXSCU_CFG_GTMDIV_300MHZ */
887 
888 #ifndef IFXSCU_CFG_ETHDIV_80MHZ
889 /** \brief Macro to configure ETHDIV at 80MHz target frequency */
890 #define IFXSCU_CFG_ETHDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ * 2)
891 #endif /*#ifndef IFXSCU_CFG_ETHDIV_80MHZ */
892 
893 #ifndef IFXSCU_CFG_ETHDIV_133MHZ
894 /** \brief Macro to configure ETHDIV at 133MHz target frequency */
895 #define IFXSCU_CFG_ETHDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 3)
896 #endif /*#ifndef IFXSCU_CFG_ETHDIV_133MHZ */
897 
898 #ifndef IFXSCU_CFG_ETHDIV_160MHZ
899 /** \brief Macro to configure ETHDIV at 160MHz target frequency */
900 #define IFXSCU_CFG_ETHDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 4)
901 #endif /*#ifndef IFXSCU_CFG_ETHDIV_160MHZ */
902 
903 #ifndef IFXSCU_CFG_ETHDIV_200MHZ
904 /** \brief Macro to configure ETHDIV at 200MHz target frequency */
905 #define IFXSCU_CFG_ETHDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 4)
906 #endif /*#ifndef IFXSCU_CFG_ETHDIV_200MHZ */
907 
908 #ifndef IFXSCU_CFG_ETHDIV_240MHZ
909 /** \brief Macro to configure ETHDIV at 240MHz target frequency */
910 #define IFXSCU_CFG_ETHDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 5)
911 #endif /*#ifndef IFXSCU_CFG_ETHDIV_240MHZ */
912 
913 #ifndef IFXSCU_CFG_ETHDIV_300MHZ
914 /** \brief Macro to configure ETHDIV at 300MHz target frequency */
915 #define IFXSCU_CFG_ETHDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 6)
916 #endif /*#ifndef IFXSCU_CFG_ETHDIV_300MHZ */
917 
918 #ifndef IFXSCU_CFG_ASCLINFDIV_80MHZ
919 /** \brief Macro to configure ASCLINFDIV at 80MHz target frequency */
920 #define IFXSCU_CFG_ASCLINFDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
921 #endif /*#ifndef IFXSCU_CFG_ASCLINFDIV_80MHZ */
922 
923 #ifndef IFXSCU_CFG_ASCLINFDIV_133MHZ
924 /** \brief Macro to configure ASCLINFDIV at 133MHz target frequency */
925 #define IFXSCU_CFG_ASCLINFDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
926 #endif /*#ifndef IFXSCU_CFG_ASCLINFDIV_133MHZ */
927 
928 #ifndef IFXSCU_CFG_ASCLINFDIV_160MHZ
929 /** \brief Macro to configure ASCLINFDIV at 160MHz target frequency */
930 #define IFXSCU_CFG_ASCLINFDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
931 #endif /*#ifndef IFXSCU_CFG_ASCLINFDIV_160MHZ */
932 
933 #ifndef IFXSCU_CFG_ASCLINFDIV_200MHZ
934 /** \brief Macro to configure ASCLINFDIV at 200MHz target frequency */
935 #define IFXSCU_CFG_ASCLINFDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
936 #endif /*#ifndef IFXSCU_CFG_ASCLINFDIV_200MHZ */
937 
938 #ifndef IFXSCU_CFG_ASCLINFDIV_240MHZ
939 /** \brief Macro to configure ASCLINFDIV at 240MHz target frequency */
940 #define IFXSCU_CFG_ASCLINFDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
941 #endif /*#ifndef IFXSCU_CFG_ASCLINFDIV_240MHZ */
942 
943 #ifndef IFXSCU_CFG_ASCLINFDIV_300MHZ
944 /** \brief Macro to configure ASCLINFDIV at 300MHz target frequency */
945 #define IFXSCU_CFG_ASCLINFDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
946 #endif /*#ifndef IFXSCU_CFG_ASCLINFDIV_300MHZ */
947 
948 #ifndef IFXSCU_CFG_ASCLINSDIV_80MHZ
949 /** \brief Macro to configure ASCLINSDIV at 80MHz target frequency */
950 #define IFXSCU_CFG_ASCLINSDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
951 #endif /*#ifndef IFXSCU_CFG_ASCLINSDIV_80MHZ */
952 
953 #ifndef IFXSCU_CFG_ASCLINSDIV_133MHZ
954 /** \brief Macro to configure ASCLINSDIV at 133MHz target frequency */
955 #define IFXSCU_CFG_ASCLINSDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
956 #endif /*#ifndef IFXSCU_CFG_ASCLINSDIV_133MHZ */
957 
958 #ifndef IFXSCU_CFG_ASCLINSDIV_160MHZ
959 /** \brief Macro to configure ASCLINSDIV at 160MHz target frequency */
960 #define IFXSCU_CFG_ASCLINSDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
961 #endif /*#ifndef IFXSCU_CFG_ASCLINSDIV_160MHZ */
962 
963 #ifndef IFXSCU_CFG_ASCLINSDIV_200MHZ
964 /** \brief Macro to configure ASCLINSDIV at 200MHz target frequency */
965 #define IFXSCU_CFG_ASCLINSDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
966 #endif /*#ifndef IFXSCU_CFG_ASCLINSDIV_200MHZ */
967 
968 #ifndef IFXSCU_CFG_ASCLINSDIV_240MHZ
969 /** \brief Macro to configure ASCLINSDIV at 240MHz target frequency */
970 #define IFXSCU_CFG_ASCLINSDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
971 #endif /*#ifndef IFXSCU_CFG_ASCLINSDIV_240MHZ */
972 
973 #ifndef IFXSCU_CFG_ASCLINSDIV_300MHZ
974 /** \brief Macro to configure ASCLINSDIV at 300MHz target frequency */
975 #define IFXSCU_CFG_ASCLINSDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
976 #endif /*#ifndef IFXSCU_CFG_ASCLINSDIV_200MHZ */
977 
978 #ifndef IFXSCU_CFG_BBBDIV_80MHZ
979 /** \brief Macro to configure BBBDIV at 80MHz target frequency */
980 #define IFXSCU_CFG_BBBDIV_80MHZ (IFXSCU_CFG_SRIDIV_80MHZ * 2)
981 #endif /*#ifndef IFXSCU_CFG_BBBDIV_80MHZ */
982 
983 #ifndef IFXSCU_CFG_BBBDIV_133MHZ
984 /** \brief Macro to configure BBBDIV at 133MHz target frequency */
985 #define IFXSCU_CFG_BBBDIV_133MHZ (IFXSCU_CFG_SRIDIV_133MHZ * 2)
986 #endif /*#ifndef IFXSCU_CFG_BBBDIV_133MHZ */
987 
988 #ifndef IFXSCU_CFG_BBBDIV_160MHZ
989 /** \brief Macro to configure BBBDIV at 160MHz target frequency */
990 #define IFXSCU_CFG_BBBDIV_160MHZ (IFXSCU_CFG_SRIDIV_160MHZ * 2)
991 #endif /*#ifndef IFXSCU_CFG_BBBDIV_160MHZ */
992 
993 #ifndef IFXSCU_CFG_BBBDIV_200MHZ
994 /** \brief Macro to configure BBBDIV at 200MHz target frequency */
995 #define IFXSCU_CFG_BBBDIV_200MHZ (IFXSCU_CFG_SRIDIV_200MHZ * 2)
996 #endif /*#ifndef IFXSCU_CFG_BBBDIV_200MHZ */
997 
998 #ifndef IFXSCU_CFG_BBBDIV_240MHZ
999 /** \brief Macro to configure BBBDIV at 240MHz target frequency */
1000 #define IFXSCU_CFG_BBBDIV_240MHZ (IFXSCU_CFG_SRIDIV_240MHZ * 2)
1001 #endif /*#ifndef IFXSCU_CFG_BBBDIV_240MHZ */
1002 
1003 #ifndef IFXSCU_CFG_BBBDIV_300MHZ
1004 /** \brief Macro to configure BBBDIV at 300MHz target frequency */
1005 #define IFXSCU_CFG_BBBDIV_300MHZ (IFXSCU_CFG_SRIDIV_300MHZ * 2)
1006 #endif /*#ifndef IFXSCU_CFG_BBBDIV_300MHZ */
1007 
1008 #ifndef IFXSCU_CFG_CPU0DIV_80MHZ
1009 /** \brief Macro to configure CPU0DIV at 80MHz target frequency */
1010 #define IFXSCU_CFG_CPU0DIV_80MHZ (0) /*Same as SRIDIV */
1011 #endif /*#ifndef IFXSCU_CFG_CPU0DIV_80MHZ */
1012 
1013 #ifndef IFXSCU_CFG_CPU0DIV_133MHZ
1014 /** \brief Macro to configure CPU0DIV at 133MHz target frequency */
1015 #define IFXSCU_CFG_CPU0DIV_133MHZ (0) /*Same as SRIDIV */
1016 #endif /*#ifndef IFXSCU_CFG_CPU0DIV_133MHZ */
1017 
1018 #ifndef IFXSCU_CFG_CPU0DIV_160MHZ
1019 /** \brief Macro to configure CPU0DIV at 160MHz target frequency */
1020 #define IFXSCU_CFG_CPU0DIV_160MHZ (0) /*Same as SRIDIV */
1021 #endif /*#ifndef IFXSCU_CFG_CPU0DIV_160MHZ */
1022 
1023 #ifndef IFXSCU_CFG_CPU0DIV_200MHZ
1024 /** \brief Macro to configure CPU0DIV at 200MHz target frequency */
1025 #define IFXSCU_CFG_CPU0DIV_200MHZ (0) /*Same as SRIDIV */
1026 #endif /*#ifndef IFXSCU_CFG_CPU0DIV_200MHZ */
1027 
1028 #ifndef IFXSCU_CFG_CPU0DIV_240MHZ
1029 /** \brief Macro to configure CPU0DIV at 240MHz target frequency */
1030 #define IFXSCU_CFG_CPU0DIV_240MHZ (0) /*Same as SRIDIV */
1031 #endif /*#ifndef IFXSCU_CFG_CPU0DIV_240MHZ */
1032 
1033 #ifndef IFXSCU_CFG_CPU0DIV_300MHZ
1034 /** \brief Macro to configure CPU0DIV at 300MHz target frequency */
1035 #define IFXSCU_CFG_CPU0DIV_300MHZ (0) /*Same as SRIDIV */
1036 #endif /*#ifndef IFXSCU_CFG_CPU0DIV_300MHZ */
1037 
1038 #ifndef IFXSCU_CFG_CPU1DIV_80MHZ
1039 /** \brief Macro to configure CPU1DIV at 80MHz target frequency */
1040 #define IFXSCU_CFG_CPU1DIV_80MHZ (0) /*Same as SRIDIV */
1041 #endif /*#ifndef IFXSCU_CFG_CPU1DIV_80MHZ */
1042 
1043 #ifndef IFXSCU_CFG_CPU1DIV_133MHZ
1044 /** \brief Macro to configure CPU1DIV at 133MHz target frequency */
1045 #define IFXSCU_CFG_CPU1DIV_133MHZ (0) /*Same as SRIDIV */
1046 #endif /*#ifndef IFXSCU_CFG_CPU1DIV_133MHZ */
1047 
1048 #ifndef IFXSCU_CFG_CPU1DIV_160MHZ
1049 /** \brief Macro to configure CPU1DIV at 160MHz target frequency */
1050 #define IFXSCU_CFG_CPU1DIV_160MHZ (0) /*Same as SRIDIV */
1051 #endif /*#ifndef IFXSCU_CFG_CPU1DIV_160MHZ */
1052 
1053 #ifndef IFXSCU_CFG_CPU1DIV_200MHZ
1054 /** \brief Macro to configure CPU1DIV at 200MHz target frequency */
1055 #define IFXSCU_CFG_CPU1DIV_200MHZ (0) /*Same as SRIDIV */
1056 #endif /*#ifndef IFXSCU_CFG_CPU1DIV_200MHZ */
1057 
1058 #ifndef IFXSCU_CFG_CPU1DIV_240MHZ
1059 /** \brief Macro to configure CPU1DIV at 240MHz target frequency */
1060 #define IFXSCU_CFG_CPU1DIV_240MHZ (0) /*Same as SRIDIV */
1061 #endif /*#ifndef IFXSCU_CFG_CPU1DIV_240MHZ */
1062 
1063 #ifndef IFXSCU_CFG_CPU1DIV_300MHZ
1064 /** \brief Macro to configure CPU1DIV at 300MHz target frequency */
1065 #define IFXSCU_CFG_CPU1DIV_300MHZ (0) /*Same as SRIDIV */
1066 #endif /*#ifndef IFXSCU_CFG_CPU1DIV_300MHZ */
1067 
1068 #ifndef IFXSCU_CFG_CPU2DIV_80MHZ
1069 /** \brief Macro to configure CPU2DIV at 80MHz target frequency */
1070 #define IFXSCU_CFG_CPU2DIV_80MHZ (0) /*Same as SRIDIV */
1071 #endif /*#ifndef IFXSCU_CFG_CPU2DIV_80MHZ */
1072 
1073 #ifndef IFXSCU_CFG_CPU2DIV_133MHZ
1074 /** \brief Macro to configure CPU2DIV at 133MHz target frequency */
1075 #define IFXSCU_CFG_CPU2DIV_133MHZ (0) /*Same as SRIDIV */
1076 #endif /*#ifndef IFXSCU_CFG_CPU2DIV_133MHZ */
1077 
1078 #ifndef IFXSCU_CFG_CPU2DIV_160MHZ
1079 /** \brief Macro to configure CPU2DIV at 160MHz target frequency */
1080 #define IFXSCU_CFG_CPU2DIV_160MHZ (0) /*Same as SRIDIV */
1081 #endif /*#ifndef IFXSCU_CFG_CPU2DIV_160MHZ */
1082 
1083 #ifndef IFXSCU_CFG_CPU2DIV_200MHZ
1084 /** \brief Macro to configure CPU2DIV at 200MHz target frequency */
1085 #define IFXSCU_CFG_CPU2DIV_200MHZ (0) /*Same as SRIDIV */
1086 #endif /*#ifndef IFXSCU_CFG_CPU2DIV_200MHZ */
1087 
1088 #ifndef IFXSCU_CFG_CPU2DIV_240MHZ
1089 /** \brief Macro to configure CPU2DIV at 240MHz target frequency */
1090 #define IFXSCU_CFG_CPU2DIV_240MHZ (0) /*Same as SRIDIV */
1091 #endif /*#ifndef IFXSCU_CFG_CPU2DIV_240MHZ */
1092 
1093 #ifndef IFXSCU_CFG_CPU2DIV_300MHZ
1094 /** \brief Macro to configure CPU2DIV at 300MHz target frequency */
1095 #define IFXSCU_CFG_CPU2DIV_300MHZ (0) /*Same as SRIDIV */
1096 #endif /*#ifndef IFXSCU_CFG_CPU2DIV_300MHZ */
1097 
1098 /** \brief Macros to configure FLASH.FCON register for flash waitstate configuration.
1099  * \ref IfxScu_InitialStepConfig
1100  */
1101 
1102 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_80MHZ
1103 /** \brief Macro to configure FCON.WSPFLASH at 80MHz target frequency */
1104 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_80MHZ (3 - 1)
1105 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_80MHZ */
1106 
1107 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_133MHZ
1108 /** \brief Macro to configure FCON.WSPFLASH at 133MHz target frequency */
1109 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_133MHZ (4 - 1)
1110 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_133MHZ */
1111 
1112 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_160MHZ
1113 /** \brief Macro to configure FCON.WSPFLASH at 160MHz target frequency */
1114 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_160MHZ (5 - 1)
1115 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_160MHZ */
1116 
1117 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_200MHZ
1118 /** \brief Macro to configure FCON.WSPFLASH at 200MHz target frequency */
1119 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_200MHZ (6 - 1)
1120 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_200MHZ */
1121 
1122 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_240MHZ
1123 /** \brief Macro to configure FCON.WSPFLASH at 240MHz target frequency */
1124 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_240MHZ (8 - 1)
1125 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_240MHZ */
1126 
1127 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_300MHZ
1128 /** \brief Macro to configure FCON.WSPFLASH at 300MHz target frequency */
1129 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_300MHZ (9 - 1)
1130 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_300MHZ */
1131 
1132 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_80MHZ
1133 /** \brief Macro to configure FCON.WSECP_ at 80MHz target frequency */
1134 #define IFXSCU_CFG_FLASH_FCON_WSECPF_80MHZ (1 - 1)
1135 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_80MHZ */
1136 
1137 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_133MHZ
1138 /** \brief Macro to configure FCON.WSECPF at 133MHz target frequency */
1139 #define IFXSCU_CFG_FLASH_FCON_WSECPF_133MHZ (2 - 1)
1140 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_133MHZ */
1141 
1142 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_160MHZ
1143 /** \brief Macro to configure FCON.WSECPF at 160MHz target frequency */
1144 #define IFXSCU_CFG_FLASH_FCON_WSECPF_160MHZ (2 - 1)
1145 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_160MHZ */
1146 
1147 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_200MHZ
1148 /** \brief Macro to configure FCON.WSECPF at 200MHz target frequency */
1149 #define IFXSCU_CFG_FLASH_FCON_WSECPF_200MHZ (2 - 1)
1150 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_200MHZ */
1151 
1152 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_240MHZ
1153 /** \brief Macro to configure FCON.WSECPF_ at 240MHz target frequency */
1154 #define IFXSCU_CFG_FLASH_FCON_WSECPF_240MHZ (3 - 1)
1155 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_240MHZ */
1156 
1157 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_300MHZ
1158 /** \brief Macro to configure FCON.WSECPF at 300MHz target frequency */
1159 #define IFXSCU_CFG_FLASH_FCON_WSECPF_300MHZ (3 - 1)
1160 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_300MHZ */
1161 
1162 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_80MHZ
1163 /** \brief Macro to configure FCON.WSDFLASH at 80MHz target frequency */
1164 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_80MHZ (16 - 1)
1165 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_80MHZ */
1166 
1167 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_133MHZ
1168 /** \brief Macro to configure FCON.WSDFLASH_ at 133MHz target frequency, where fSRI= 133/2= 66.5MHZ */
1169 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_133MHZ (14 - 1)
1170 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_133MHZ */
1171 
1172 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_160MHZ
1173 /** \brief Macro to configure FCON.WSDFLASH at 160MHz target frequency, where fSRI= 160/2= 80MHZ */
1174 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_160MHZ (16 - 1)
1175 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_160MHZ */
1176 
1177 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_200MHZ
1178 /** \brief Macro to configure FCON.WSDFLASH at 200MHz target frequency, where fSRI= 200/2= 100MHZ */
1179 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_200MHZ (20 - 1)
1180 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_200MHZ */
1181 
1182 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_240MHZ
1183 /** \brief Macro to configure FCON.WSDFLASH at 240MHz target frequency, where fSRI= 240/3= 80MHZ */
1184 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_240MHZ (16 - 1)
1185 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_240MHZ */
1186 
1187 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_300MHZ
1188 /** \brief Macro to configure FCON.WSDFLASH at 300MHz target frequency, where fSRI= 300/3= 100MHZ */
1189 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_300MHZ (20 - 1)
1190 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_300MHZ */
1191 
1192 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_80MHZ
1193 /** \brief Macro to configure FCON.WSECDF at 80MHz target frequency */
1194 #define IFXSCU_CFG_FLASH_FCON_WSECDF_80MHZ (2 - 1)
1195 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_80MHZ */
1196 
1197 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_133MHZ
1198 /** \brief Macro to configure FCON.WSECDF at 133MHz target frequency, where fSRI= 133/2= 66.5MHZ */
1199 #define IFXSCU_CFG_FLASH_FCON_WSECDF_133MHZ (2 - 1)
1200 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_133MHZ */
1201 
1202 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_160MHZ
1203 /** \brief Macro to configure FCON.WSECDF at 160MHz target frequency, where fSRI= 160/2= 80MHZ */
1204 #define IFXSCU_CFG_FLASH_FCON_WSECDF_160MHZ (2 - 1)
1205 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_160MHZ */
1206 
1207 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_200MHZ
1208 /** \brief Macro to configure FCON.WSECDF at 200MHz target frequency, where fSRI= 200/2= 100MHZ */
1209 #define IFXSCU_CFG_FLASH_FCON_WSECDF_200MHZ (2 - 1)
1210 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_200MHZ */
1211 
1212 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_240MHZ
1213 /** \brief Macro to configure FCON.WSECDF at 240MHz target frequency, where fSRI= 240/3= 80MHZ */
1214 #define IFXSCU_CFG_FLASH_FCON_WSECDF_240MHZ (2 - 1)
1215 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_240MHZ */
1216 
1217 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_300MHZ
1218 /** \brief Macro to configure FCON.WSECDF at 300MHz target frequency, where fSRI= 300/3= 100MHZ */
1219 #define IFXSCU_CFG_FLASH_FCON_WSECDF_300MHZ (2 - 1)
1220 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_300MHZ */
1221 
1222 /** \brief Macros to configure FLASH.FCON registers */
1223 #define IFXSCU_CFG_FLASH_WAITSTATE_MSK \
1224  ( \
1225  (IFX_FLASH_FCON_WSPFLASH_MSK << IFX_FLASH_FCON_WSPFLASH_OFF) | \
1226  (IFX_FLASH_FCON_WSECPF_MSK << IFX_FLASH_FCON_WSECPF_OFF) | \
1227  (IFX_FLASH_FCON_WSDFLASH_MSK << IFX_FLASH_FCON_WSDFLASH_OFF) | \
1228  (IFX_FLASH_FCON_WSECDF_MSK << IFX_FLASH_FCON_WSECDF_OFF))
1229 
1230 #define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_(pllFreq) \
1231  ( \
1232  (IFXSCU_CFG_FLASH_FCON_WSPFLASH_##pllFreq << IFX_FLASH_FCON_WSPFLASH_OFF) | \
1233  (IFXSCU_CFG_FLASH_FCON_WSECPF_##pllFreq << IFX_FLASH_FCON_WSECPF_OFF) | \
1234  (IFXSCU_CFG_FLASH_FCON_WSDFLASH_##pllFreq << IFX_FLASH_FCON_WSDFLASH_OFF) | \
1235  (IFXSCU_CFG_FLASH_FCON_WSECDF_##pllFreq << IFX_FLASH_FCON_WSECDF_OFF))
1236 
1237 #define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC(pllFreq) IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_(pllFreq)
1238 
1239 #define IFXSCU_CFG_FLASH_WAITSTATE_VAL IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC(IFXSCU_CFG_PLL_FREQ)
1240 
1241 /** \brief Macros to configure CCUCON0 Clock distribution */
1242 #define IFXSCU_CFG_CCUCON0_MASK \
1243  ( \
1244  (IFX_SCU_CCUCON0_BAUD1DIV_MSK << IFX_SCU_CCUCON0_BAUD1DIV_OFF) | \
1245  (IFX_SCU_CCUCON0_BAUD2DIV_MSK << IFX_SCU_CCUCON0_BAUD2DIV_OFF) | \
1246  (IFX_SCU_CCUCON0_SRIDIV_MSK << IFX_SCU_CCUCON0_SRIDIV_OFF) | \
1247  (IFX_SCU_CCUCON0_SPBDIV_MSK << IFX_SCU_CCUCON0_SPBDIV_OFF) | \
1248  (IFX_SCU_CCUCON0_FSI2DIV_MSK << IFX_SCU_CCUCON0_FSI2DIV_OFF) | \
1249  (IFX_SCU_CCUCON0_FSIDIV_MSK << IFX_SCU_CCUCON0_FSIDIV_OFF))
1250 
1251 #define IFXSCU_CFG_CCUCON0_BASIC_(pllFreq) \
1252  (uint32)( \
1253  (IFXSCU_CFG_BAUD1DIV_##pllFreq << IFX_SCU_CCUCON0_BAUD1DIV_OFF) | \
1254  (IFXSCU_CFG_BAUD2DIV_##pllFreq << IFX_SCU_CCUCON0_BAUD2DIV_OFF) | \
1255  (IFXSCU_CFG_SRIDIV_##pllFreq << IFX_SCU_CCUCON0_SRIDIV_OFF) | \
1256  (IFXSCU_CFG_SPBDIV_##pllFreq << IFX_SCU_CCUCON0_SPBDIV_OFF) | \
1257  (IFXSCU_CFG_FSI2DIV_##pllFreq << IFX_SCU_CCUCON0_FSI2DIV_OFF) | \
1258  (IFXSCU_CFG_FSIDIV_##pllFreq << IFX_SCU_CCUCON0_FSIDIV_OFF))
1259 
1260 #define IFXSCU_CFG_CCUCON0_BASIC(pllFreq) IFXSCU_CFG_CCUCON0_BASIC_(pllFreq)
1261 
1262 #define IFXSCU_CFG_CCUCON0 IFXSCU_CFG_CCUCON0_BASIC(IFXSCU_CFG_PLL_FREQ)
1263 
1264 /** \brief Macros to configure CCUCON1 Clock distribution */
1265 #define IFXSCU_CFG_CCUCON1_MASK \
1266  ( \
1267  (IFX_SCU_CCUCON1_CANDIV_MSK << IFX_SCU_CCUCON1_CANDIV_OFF) | \
1268  (IFX_SCU_CCUCON1_ERAYDIV_MSK << IFX_SCU_CCUCON1_ERAYDIV_OFF) | \
1269  (IFX_SCU_CCUCON1_STMDIV_MSK << IFX_SCU_CCUCON1_STMDIV_OFF) | \
1270  (IFX_SCU_CCUCON1_GTMDIV_MSK << IFX_SCU_CCUCON1_GTMDIV_OFF) | \
1271  (IFX_SCU_CCUCON1_ETHDIV_MSK << IFX_SCU_CCUCON1_ETHDIV_OFF) | \
1272  (IFX_SCU_CCUCON1_ASCLINFDIV_MSK << IFX_SCU_CCUCON1_ASCLINFDIV_OFF) | \
1273  (IFX_SCU_CCUCON1_ASCLINSDIV_MSK << IFX_SCU_CCUCON1_ASCLINSDIV_OFF))
1274 
1275 #define IFXSCU_CFG_CCUCON1_BASIC_(pllFreq) \
1276  (uint32)( \
1277  (IFXSCU_CFG_CANDIV_##pllFreq << IFX_SCU_CCUCON1_CANDIV_OFF) | \
1278  (IFXSCU_CFG_ERAYDIV_80MHZ << IFX_SCU_CCUCON1_ERAYDIV_OFF) | \
1279  (IFXSCU_CFG_STMDIV_##pllFreq << IFX_SCU_CCUCON1_STMDIV_OFF) | \
1280  (IFXSCU_CFG_GTMDIV_##pllFreq << IFX_SCU_CCUCON1_GTMDIV_OFF) | \
1281  (IFXSCU_CFG_ETHDIV_##pllFreq << IFX_SCU_CCUCON1_ETHDIV_OFF) | \
1282  (IFXSCU_CFG_ASCLINFDIV_##pllFreq << IFX_SCU_CCUCON1_ASCLINFDIV_OFF) | \
1283  (IFXSCU_CFG_ASCLINSDIV_##pllFreq << IFX_SCU_CCUCON1_ASCLINSDIV_OFF))
1284 
1285 #define IFXSCU_CFG_CCUCON1_BASIC(pllFreq) IFXSCU_CFG_CCUCON1_BASIC_(pllFreq)
1286 
1287 #define IFXSCU_CFG_CCUCON1 IFXSCU_CFG_CCUCON1_BASIC(IFXSCU_CFG_PLL_FREQ)
1288 
1289 /** \brief Macros to configure CCUCON2 Clock distribution */
1290 #define IFXSCU_CFG_CCUCON2_MASK \
1291  ( \
1292  (IFX_SCU_CCUCON2_BBBDIV_MSK << IFX_SCU_CCUCON2_BBBDIV_OFF))
1293 
1294 #define IFXSCU_CFG_CCUCON2_BASIC_(pllFreq) \
1295  (uint32)( \
1296  (IFXSCU_CFG_BBBDIV_##pllFreq << IFX_SCU_CCUCON2_BBBDIV_OFF))
1297 
1298 #define IFXSCU_CFG_CCUCON2_BASIC(pllFreq) IFXSCU_CFG_CCUCON2_BASIC_(pllFreq)
1299 
1300 #define IFXSCU_CFG_CCUCON2 IFXSCU_CFG_CCUCON2_BASIC(IFXSCU_CFG_PLL_FREQ)
1301 
1302 /** \brief Macros to configure CCUCON5 Clock distribution */
1303 #define IFXSCU_CFG_CCUCON5_MASK \
1304  ( \
1305  (IFX_SCU_CCUCON5_MAXDIV_MSK << IFX_SCU_CCUCON5_MAXDIV_OFF))
1306 
1307 #define IFXSCU_CFG_CCUCON5_BASIC_(pllFreq) \
1308  (uint32)( \
1309  (IFXSCU_CFG_MAXDIV_##pllFreq << IFX_SCU_CCUCON5_MAXDIV_OFF))
1310 
1311 #define IFXSCU_CFG_CCUCON5_BASIC(pllFreq) IFXSCU_CFG_CCUCON5_BASIC_(pllFreq)
1312 
1313 #define IFXSCU_CFG_CCUCON5 IFXSCU_CFG_CCUCON5_BASIC(IFXSCU_CFG_PLL_FREQ)
1314 
1315 /** \brief Macros to configure CCUCON6 Clock distribution */
1316 #define IFXSCU_CFG_CCUCON6_MASK \
1317  ( \
1318  (IFX_SCU_CCUCON6_CPU0DIV_MSK << IFX_SCU_CCUCON6_CPU0DIV_OFF))
1319 
1320 #define IFXSCU_CFG_CCUCON6_BASIC_(pllFreq) \
1321  (uint32)( \
1322  (IFXSCU_CFG_CPU0DIV_##pllFreq << IFX_SCU_CCUCON6_CPU0DIV_OFF))
1323 
1324 #define IFXSCU_CFG_CCUCON6_BASIC(pllFreq) IFXSCU_CFG_CCUCON6_BASIC_(pllFreq)
1325 
1326 #define IFXSCU_CFG_CCUCON6 IFXSCU_CFG_CCUCON6_BASIC(IFXSCU_CFG_PLL_FREQ)
1327 
1328 /** \brief Macros to configure CCUCON7 Clock distribution */
1329 #define IFXSCU_CFG_CCUCON7_MASK \
1330  ( \
1331  (IFX_SCU_CCUCON7_CPU1DIV_MSK << IFX_SCU_CCUCON7_CPU1DIV_OFF))
1332 
1333 #define IFXSCU_CFG_CCUCON7_BASIC_(pllFreq) \
1334  (uint32)( \
1335  (IFXSCU_CFG_CPU1DIV_##pllFreq << IFX_SCU_CCUCON7_CPU1DIV_OFF))
1336 
1337 #define IFXSCU_CFG_CCUCON7_BASIC(pllFreq) IFXSCU_CFG_CCUCON7_BASIC_(pllFreq)
1338 
1339 #define IFXSCU_CFG_CCUCON7 IFXSCU_CFG_CCUCON7_BASIC(IFXSCU_CFG_PLL_FREQ)
1340 
1341 /** \brief Macros to configure CCUCON8 Clock distribution */
1342 #define IFXSCU_CFG_CCUCON8_MASK \
1343  ( \
1344  (IFX_SCU_CCUCON8_CPU2DIV_MSK << IFX_SCU_CCUCON8_CPU2DIV_OFF))
1345 
1346 #define IFXSCU_CFG_CCUCON8_BASIC_(pllFreq) \
1347  (uint32)( \
1348  (IFXSCU_CFG_CPU2DIV_##pllFreq << IFX_SCU_CCUCON8_CPU2DIV_OFF))
1349 
1350 #define IFXSCU_CFG_CCUCON8_BASIC(pllFreq) IFXSCU_CFG_CCUCON8_BASIC_(pllFreq)
1351 
1352 #define IFXSCU_CFG_CCUCON8 IFXSCU_CFG_CCUCON8_BASIC(IFXSCU_CFG_PLL_FREQ)
1353 
1354 #define IFXSCU_CFG_CLK_DISTRIBUTION \
1355  { \
1356 /* { uint32 value, uint32 mask }*/ \
1357  {IFXSCU_CFG_CCUCON0, IFXSCU_CFG_CCUCON0_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon0;*/ \
1358  {IFXSCU_CFG_CCUCON1, IFXSCU_CFG_CCUCON1_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon1;*/ \
1359  {IFXSCU_CFG_CCUCON2, IFXSCU_CFG_CCUCON2_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon2;*/ \
1360  {IFXSCU_CFG_CCUCON5, IFXSCU_CFG_CCUCON5_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon5;*/ \
1361  {IFXSCU_CFG_CCUCON6, IFXSCU_CFG_CCUCON6_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon6;*/ \
1362  {IFXSCU_CFG_CCUCON7, IFXSCU_CFG_CCUCON7_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon7;*/ \
1363  {IFXSCU_CFG_CCUCON8, IFXSCU_CFG_CCUCON8_MASK} /*IfxScuCcu_CcuconRegConfig ccucon8;*/ \
1364  }
1365 
1366 /*Utility macros for the configuration structure */
1367 /*macro for pll steps configuration */
1368 #define IFXSCU_CFG_PLL_STEPS_BASIC_(xtalFreq, pllFreq) IFXSCU_CFG_PLL_STEPS_##xtalFreq##_##pllFreq
1369 #define IFXSCU_CFG_PLL_STEPS_BASIC(xtalFreq, pllFreq) IFXSCU_CFG_PLL_STEPS_BASIC_(xtalFreq, pllFreq)
1370 #define IFXSCU_CFG_PLL_STEPS IFXSCU_CFG_PLL_STEPS_BASIC(IFXSCU_CFG_XTAL_FREQ, IFXSCU_CFG_PLL_FREQ)
1371 
1372 /*macro for pll initial step configuration */
1373 #define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_(xtalFreq, pllFreq) IFXSCU_CFG_PLL_INITIAL_STEP_##xtalFreq##_##pllFreq
1374 #define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC(xtalFreq, pllFreq) IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_(xtalFreq, pllFreq)
1375 #define IFXSCU_CFG_PLL_INITIAL_STEP IFXSCU_CFG_PLL_INITIAL_STEP_BASIC(IFXSCU_CFG_XTAL_FREQ, IFXSCU_CFG_PLL_FREQ)
1376 
1377 #define IFXSCU_CFG_FLASH_WAITSTATE \
1378 /* { uint32 value, uint32 mask }*/\
1379  {IFXSCU_CFG_FLASH_WAITSTATE_VAL, IFXSCU_CFG_FLASH_WAITSTATE_MSK}
1380 
1381 #if (IFX_CFG_SCU_XTAL_FREQUENCY == (20000000))
1382 #define IFXSCU_CFG_XTAL_FREQ 20MHZ
1383 #elif (IFX_CFG_SCU_XTAL_FREQUENCY == (40000000))
1384 #define IFXSCU_CFG_XTAL_FREQ 40MHZ
1385 #elif (IFX_CFG_SCU_XTAL_FREQUENCY == (16000000))
1386 #define IFXSCU_CFG_XTAL_FREQ 16MHZ
1387 #elif (IFX_CFG_SCU_XTAL_FREQUENCY == (8000000))
1388 #define IFXSCU_CFG_XTAL_FREQ 8MHZ
1389 #else
1390 #error "Wrong XTAL frequency configuration! check IFX_CFG_SCU_XTAL_FREQUENCY configuration in Ifx_Cfg.h."
1391 #error "Aurix Triboard supported crystal frequencies are 8MHz, 16MHz, 20MHz and 40MHz"
1392 #endif
1393 
1394 #if (IFX_CFG_SCU_PLL_FREQUENCY == (80000000))
1395 #define IFXSCU_CFG_PLL_FREQ 80MHZ
1396 #elif (IFX_CFG_SCU_PLL_FREQUENCY == (133000000)) && (IFX_CFG_SCU_XTAL_FREQUENCY != (8000000))
1397 #define IFXSCU_CFG_PLL_FREQ 133MHZ
1398 #elif (IFX_CFG_SCU_PLL_FREQUENCY == (160000000))
1399 #define IFXSCU_CFG_PLL_FREQ 160MHZ
1400 #elif (IFX_CFG_SCU_PLL_FREQUENCY == (200000000))
1401 #define IFXSCU_CFG_PLL_FREQ 200MHZ
1402 #else
1403 #error "Wrong PLL frequency configuration!, check IFX_CFG_SCU_PLL_FREQUENCY configuration in Ifx_Cfg.h."
1404 #error "Supported PLL frequencies are 80MHz, 133MHz (8MHz XTAL doesn't support), 160Mhz, and 200MHz."
1405 #endif
1406 
1407 /******************************************************************************/
1408 /* Enum */
1409 /******************************************************************************/
1410 /** Clock selection */
1411 typedef enum
1412 {
1413  IfxScu_CCUCON0_CLKSEL_fBack = 0,
1414  IfxScu_CCUCON0_CLKSEL_fPll = 1
1415 } IfxScu_CCUCON0_CLKSEL;
1416 
1417 /** Input selection for PLL and PLL ERAY */
1418 typedef enum
1419 {
1420  IfxScu_CCUCON1_INSEL_fOsc1 = 0,
1421  IfxScu_CCUCON1_INSEL_fOsc0 = 1
1422 } IfxScu_CCUCON1_INSEL;
1423 
1424 /** Input frequency request control */
1425 typedef enum
1426 {
1427  IfxScu_WDTCON1_IR_divBy16384 = 0,
1428  IfxScu_WDTCON1_IR_divBy256 = 1,
1429  IfxScu_WDTCON1_IR_divBy64 = 2
1430 } IfxScu_WDTCON1_IR;
1431 
1432 typedef enum
1433 {
1434  IfxScu_PMCSR_REQSLP_Run = 0U, /* 00 Request CPU Run Mode */
1435  IfxScu_PMCSR_REQSLP_Idle = 1U, /* 01 Request CPU Idle Mode */
1436  IfxScu_PMCSR_REQSLP_Sleep = 2U, /* 10 Request CPU System Sleep Mode */
1437  IfxScu_PMCSR_REQSLP_Stby = 3U /* 11 Request System Standby Mode */
1438 } IfxScu_PMCSR_REQSLP;
1439 
1440 /******************************************************************************/
1441 
1442 #endif /* IFXSCU_CFG_H */