iLLD_TC27xD  1.0
IfxMtu.c
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1 /**
2  * \file IfxMtu.c
3  * \brief MTU basic functionality
4  *
5  * \version iLLD_1_0_0_11_0
6  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  *
24  */
25 
26 /******************************************************************************/
27 /*----------------------------------Includes----------------------------------*/
28 /******************************************************************************/
29 
30 #include "IfxMtu.h"
31 
32 /** \addtogroup IfxLld_Mtu_Std_Utility
33  * \{ */
34 
35 /******************************************************************************/
36 /*-----------------------Private Function Prototypes--------------------------*/
37 /******************************************************************************/
38 
39 /** \brief API to wait for requested tower depth.
40  * \param towerDepth tower depth of MBIST Ram
41  * \param numInstructions number of instructions
42  * \param mbistSel Memory Selection
43  * \return None
44  */
45 static void IfxMtu_waitForMbistDone(uint32 towerDepth, uint8 numInstructions, IfxMtu_MbistSel mbistSel);
46 
47 /** \} */
48 
49 /******************************************************************************/
50 /*-------------------------Function Implementations---------------------------*/
51 /******************************************************************************/
52 
53 void IfxMtu_clearErrorTracking(IfxMtu_MbistSel mbistSel)
54 {
55  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
56  mc->ECCD.U |= (1 << IFX_MC_ECCD_TRC_OFF);
57 }
58 
59 
60 void IfxMtu_clearSram(IfxMtu_MbistSel mbistSel)
61 {
62  uint8 isEndInitEnabled = 0;
63  uint16 password = 0;
64 
65  password = IfxScuWdt_getSafetyWatchdogPassword();
66 
67  /* Check if the Endinit is cleared by application. If not, then handle it internally inside teh function.*/
68  if (IfxScuWdt_getSafetyWatchdogEndInit() == 1U)
69  {
70  /* Clear EndInit */
71  IfxScuWdt_clearSafetyEndinit(password);
72  isEndInitEnabled = 1;
73  }
74 
75  IfxMtu_clearSramStart(mbistSel);
76 
77  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
78  IfxScuWdt_setSafetyEndinit(password);
79 
80  /* wait for the end of the fill operation */
81  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
82  IfxMtu_waitForMbistDone(IfxMtu_sramTable[mbistSel].mbistDelay, 1, mbistSel);
83  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, mc->MSTATUS.B.DONE != 0);
84 
85  while (!IfxMtu_isMbistDone(mbistSel))
86  {
87  __nop();
88  }
89 
90  /* Clear EndInit */
91  IfxScuWdt_clearSafetyEndinit(password);
92 
93  IfxMtu_clearSramContinue(mbistSel);
94 
95  if (isEndInitEnabled == 1)
96  {
97  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
98  IfxScuWdt_setSafetyEndinit(password);
99  }
100 }
101 
102 
103 void IfxMtu_clearSramContinue(IfxMtu_MbistSel mbistSel)
104 {
105  /* Before clearing the ECC error flags we've to issue a dummy SRAM access to get a valid memory output */
106  IfxMtu_readSramAddress(mbistSel, 0x0000);
107 
108  /* Note: a SMU alarm will be flagged HERE if the wrong ECC has been written! */
109  IfxMtu_disableMbistShell(mbistSel);
110 
111  /* for auto-init memories: wait for the end of the clear operation */
112  while (IfxMtu_isAutoInitRunning(mbistSel))
113  {}
114 }
115 
116 
117 void IfxMtu_clearSramStart(IfxMtu_MbistSel mbistSel)
118 {
119  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
120 
121  IfxMtu_enableMbistShell(mbistSel);
122 
123  /* for auto-init memories: wait for the end of the clear operation */
124  while (IfxMtu_isAutoInitRunning(mbistSel))
125  {}
126 
127  /* write valid ECC code for all-zero data into RDBFL registers */
128  {
129  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, mbistSel < IFXMTU_NUM_MBIST_TABLE_ITEMS);
130  const IfxMtu_SramItem *item = (IfxMtu_SramItem *)&IfxMtu_sramTable[mbistSel];
131 
132  uint8 numBlocks = item->numBlocks;
133  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, numBlocks > 0);
134 
135  uint16 dataSize = item->dataSize;
136  uint8 eccSize = item->eccSize;
137  uint32 eccInvPos0 = dataSize + item->eccInvPos0;
138  uint32 eccInvPos1 = dataSize + item->eccInvPos1;
139 
140  uint32 memSize = dataSize + eccSize;
141 
142  uint32 bitPos = 0;
143  uint32 wordIx = 0;
144  uint16 data = 0;
145  /* de-serialize data stream into 16bit packets */
146  uint32 mem;
147 
148  for (mem = 0; mem < numBlocks; ++mem)
149  {
150  uint32 i;
151 
152  for (i = 0; i < memSize; ++i)
153  {
154  if ((i == eccInvPos0) || (i == eccInvPos1))
155  {
156  data |= (1 << bitPos);
157  }
158 
159  ++bitPos;
160 
161  if (bitPos >= 16)
162  {
163  mc->RDBFL[wordIx++].U = data;
164  bitPos = 0;
165  data = 0;
166  }
167  }
168  }
169 
170  /* final word? */
171  if (bitPos != 0)
172  {
173  mc->RDBFL[wordIx].U = data;
174  }
175  }
176 
177  /* start fill operation */
178  uint16 mcontrolMask = 0x4000; /* set USERED flag */
179  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DINIT_OFF) | (1 << IFX_MC_MCONTROL_START_OFF); /* START = DINIT = 1 */
180  mc->MCONTROL.U = mcontrolMask | (0 << IFX_MC_MCONTROL_DINIT_OFF) | (1 << IFX_MC_MCONTROL_DINIT_OFF); /* START = 0 */
181 }
182 
183 
184 void IfxMtu_disableMbistShell(IfxMtu_MbistSel mbistSel)
185 {
186  volatile uint32 *mtuMemtest = (volatile uint32 *)((uint32)&MTU_MEMTEST0 + 4 * (mbistSel >> 5));
187  uint32 mask = 1 << (mbistSel & 0x1f);
188  *mtuMemtest &= ~mask;
189 }
190 
191 
192 void IfxMtu_enableErrorTracking(IfxMtu_MbistSel mbistSel, boolean enable)
193 {
194  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
195 
196  if (enable == FALSE)
197  {
198  mc->ECCS.U &= ~(1 << IFX_MC_ECCS_TRE_OFF);
199  }
200  else
201  {
202  mc->ECCS.U |= (1 << IFX_MC_ECCS_TRE_OFF);
203  }
204 }
205 
206 
207 void IfxMtu_enableMbistShell(IfxMtu_MbistSel mbistSel)
208 {
209  volatile uint32 *mtuMemtest = (volatile uint32 *)((uint32)&MTU_MEMTEST0 + 4 * (mbistSel >> 5));
210  uint32 mask = 1 << (mbistSel & 0x1f);
211  *mtuMemtest |= mask;
212 }
213 
214 
215 uint32 IfxMtu_getSystemAddress(IfxMtu_MbistSel mbistSel, Ifx_MC_ETRR trackedSramAddress)
216 {
217  uint32 sramAddress = trackedSramAddress.B.ADDR;
218  uint32 mbi = trackedSramAddress.B.MBI;
219  uint32 systemAddress = 0;
220 
221  switch (mbistSel)
222  {
223  case IfxMtu_MbistSel_cpu0Pspr:
224  systemAddress = 0x70100000 | ((sramAddress << 3) | ((mbi & 1) << 2));
225  break;
226 
227  case IfxMtu_MbistSel_cpu0Dspr:
228  systemAddress = 0x70000000 | ((sramAddress << 4) | ((mbi & 3) << 2));
229  break;
230 
231  case IfxMtu_MbistSel_cpu1Pspr:
232  systemAddress = 0x60100000 | ((sramAddress << 4) | ((mbi & 1) << 3));
233  break;
234 
235  case IfxMtu_MbistSel_cpu1Dspr:
236  systemAddress = 0x60000000 | ((sramAddress << 4) | ((mbi & 3) << 2));
237  break;
238 
239  case IfxMtu_MbistSel_cpu2Pspr:
240  systemAddress = 0x50100000 | ((sramAddress << 4) | ((mbi & 1) << 3));
241  break;
242 
243  case IfxMtu_MbistSel_cpu2Dspr:
244  systemAddress = 0x50000000 | ((sramAddress << 4) | ((mbi & 3) << 2));
245  break;
246 
247  case IfxMtu_MbistSel_lmu:
248  systemAddress = 0xb0000000 | (sramAddress << 3);
249  break;
250 
251  case IfxMtu_MbistSel_dma:
252  systemAddress = 0xf0012000 | ((sramAddress << 5) | ((mbi & 3) << 3));
253  break;
254 
255  default:
256  systemAddress = 0; /* unsupported address descrambling */
257  }
258 
259  return systemAddress;
260 }
261 
262 
263 uint8 IfxMtu_getTrackedSramAddresses(IfxMtu_MbistSel mbistSel, Ifx_MC_ETRR *trackedSramAddresses)
264 {
265  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
266  uint8 validFlags = (mc->ECCD.U >> IFX_MC_ECCD_VAL_OFF) & IFX_MC_ECCD_VAL_MSK;
267  uint8 numTrackedAddresses = 0;
268  int i;
269 
270 #if IFX_MC_ECCD_VAL_LEN > IFXMTU_MAX_TRACKED_ADDRESSES
271 # error "Unexpected size of VAL mask"
272 #endif
273 
274  for (i = 0; i < IFXMTU_MAX_TRACKED_ADDRESSES; ++i)
275  {
276  if (validFlags & (1 << i))
277  {
278  trackedSramAddresses[numTrackedAddresses].U = mc->ETRR[i].U;
279  ++numTrackedAddresses;
280  }
281  }
282 
283  return numTrackedAddresses;
284 }
285 
286 
287 boolean IfxMtu_isAutoInitRunning(IfxMtu_MbistSel mbistSel)
288 {
289  volatile uint32 *mtuMemstat = (volatile uint32 *)((uint32)&MTU_MEMSTAT0 + 4 * (mbistSel >> 5));
290  uint32 mask = 1 << (mbistSel & 0x1f);
291  return (*mtuMemstat & mask) != 0;
292 }
293 
294 
295 boolean IfxMtu_isErrorTrackingEnabled(IfxMtu_MbistSel mbistSel)
296 {
297  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
298  return mc->ECCS.B.TRE ? TRUE : FALSE;
299 }
300 
301 
302 boolean IfxMtu_isErrorTrackingOverflow(IfxMtu_MbistSel mbistSel)
303 {
304  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
305  return mc->ECCD.B.EOV ? TRUE : FALSE;
306 }
307 
308 
309 boolean IfxMtu_isMbistDone(IfxMtu_MbistSel mbistSel)
310 {
311  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
312  uint16 status;
313 
314  status = mc->MSTATUS.U;
315  return (boolean)(status & 0x01);
316 }
317 
318 
319 void IfxMtu_readSramAddress(IfxMtu_MbistSel mbistSel, uint16 sramAddress)
320 {
321  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
322 
323  /* configure MBIST for single read opeation */
324  uint16 mcontrolMask = 0x4000; /* set USERED flag */
325  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DIR_OFF);
326  mc->CONFIG0.U = (1 << IFX_MC_CONFIG0_NUMACCS_OFF) | (1 << IFX_MC_CONFIG0_ACCSTYPE_OFF); /* 1 read access */
327  mc->CONFIG1.U = 0; /* ensure that linear scrambling is used */
328 
329  /* Set the address to be read (RAEN = 0) */
330  mc->RANGE.U = sramAddress;
331 
332  /* Start operation */
333  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DIR_OFF) | (1 << IFX_MC_MCONTROL_START_OFF);
334  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DIR_OFF);
335 
336  /* wait for the end of the fill operation */
337  IfxMtu_waitForMbistDone(256, 1, mbistSel);
338 
339  while (!IfxMtu_isMbistDone(mbistSel))
340  {
341  __nop();
342  }
343 }
344 
345 
346 uint8 IfxMtu_runCheckerBoardTest(IfxMtu_MbistSel mbistSel, uint8 rangeSel, uint8 rangeAddrUp, uint8 rangeAddrLow, uint16 *errorAddr, uint32 numberRedundancyLines)
347 {
348  /* Select MBIST Memory Controller:
349  * Ifx_MC is a type describing structure of MBIST Memory Controller
350  * registers defined in IfxMc_regdef.h file - MC object */
351  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
352  uint32 configCheckerBoardSequence[4] = {
353  0x08001000, //up /lin/w0
354  0x08001001, //up /lin/r0
355  0x00011000, //down/lin/w1
356  0x00011001
357  }; //down/lin/r1
358  uint16 password = 0;
359  uint8 retVal = 0U;
360  uint8 testStep;
361  uint8 isEndInitEnabled = 0;
362  password = IfxScuWdt_getSafetyWatchdogPassword();
363 
364  /* Check if the Endinit is cleared by application. If not, then handle it internally inside teh function.*/
365  if (IfxScuWdt_getSafetyWatchdogEndInit() == 1U)
366  {
367  /* Clear EndInit */
368  IfxScuWdt_clearSafetyEndinit(password);
369  isEndInitEnabled = 1;
370  }
371 
372  /* Enable MBIST Memory Controller */
373  IfxMtu_enableMbistShell(mbistSel);
374 
375  /* for auto-init memories: wait for the end of the clear operation */
376  while (IfxMtu_isAutoInitRunning(mbistSel))
377  {}
378 
379  /* Set the range register */
380  mc->RANGE.U = (rangeSel << 15) | (rangeAddrUp << 7) | (rangeAddrLow << 0);
381 
382  /* Run the test */
383  for (testStep = 0; testStep < 4; ++testStep)
384  {
385  mc->CONFIG0.U = configCheckerBoardSequence[testStep] & 0x0000FFFF;
386  mc->CONFIG1.U = (configCheckerBoardSequence[testStep] & 0xFFFF0000) >> 16;
387  mc->MCONTROL.U = numberRedundancyLines ? 0x30c9 : 0x00c9; // bit and row toggle
388  mc->MCONTROL.U = numberRedundancyLines ? 0x30c8 : 0x00c8; // MCONTROL.B.START will generate a RMW which is too long for small SRAMs!
389 
390  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
391  IfxScuWdt_setSafetyEndinit(password);
392 
393  /* wait for the end of the fill operation */
394  IfxMtu_waitForMbistDone(IfxMtu_sramTable[mbistSel].mbistDelay, 4, mbistSel);
395  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, mc->MSTATUS.B.DONE != 0);
396 
397  while (!IfxMtu_isMbistDone(mbistSel))
398  {
399  __nop();
400  }
401 
402  /* Clear EndInit Again */
403  IfxScuWdt_clearSafetyEndinit(password);
404 
405  /* Check the Fail Status */
406  if (mc->MSTATUS.B.FAIL)
407  {
408  /* Test has failed, check if any un-correctable error */
409  if (mc->ECCD.B.UERR)
410  {
411  /* Read Error tracking register and return saying test failed */
412  *errorAddr = mc->ETRR[0].U;
413  retVal = 1U;
414  break;
415  }
416  }
417  }
418 
419  /* Disable Memory Controller */
420 
421  IfxMtu_disableMbistShell(mbistSel);
422 
423  while (IfxMtu_isAutoInitRunning(mbistSel))
424  {}
425 
426  if (isEndInitEnabled == 1)
427  {
428  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
429  IfxScuWdt_setSafetyEndinit(password);
430  }
431 
432  return retVal;
433 }
434 
435 
436 uint8 IfxMtu_runMarchUTest(IfxMtu_MbistSel mbistSel, uint8 rangeSel, uint8 rangeAddrUp, uint8 rangeAddrLow, uint16 *errorAddr)
437 {
438  /* Select MBIST Memory Controller:
439  * Ifx_MC is a type describing structure of MBIST Memory Controller
440  * registers defined in IfxMc_regdef.h file - MC object */
441  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
442  uint32 configMarchUSequence[6] = {
443  0x08001000, //up /lin/w0
444  0x08064005, //up /lin/r0->w1->r1->w0
445  0x08022001, //up /lin/r0->w1
446  0x00094005, //down/lin/r1->w0->r0->w1
447  0x00012001, //down/lin/r1->w0
448  0x00001001
449  }; //down/lin/r0
450  uint16 password = 0;
451  uint8 retVal = 0U;
452  uint8 testStep;
453  uint8 isEndInitEnabled = 0;
454  password = IfxScuWdt_getSafetyWatchdogPassword();
455 
456  /* Check if the Endinit is cleared by application. If not, then handle it internally inside teh function.*/
457  if (IfxScuWdt_getSafetyWatchdogEndInit() == 1U)
458  {
459  /* Clear EndInit */
460  IfxScuWdt_clearSafetyEndinit(password);
461  isEndInitEnabled = 1;
462  }
463 
464  /* Enable MBIST Memory Controller */
465  IfxMtu_enableMbistShell(mbistSel);
466 
467  /* for auto-init memories: wait for the end of the clear operation */
468  while (IfxMtu_isAutoInitRunning(mbistSel))
469  {}
470 
471  /* Set the range register */
472  mc->RANGE.U = (rangeSel << 15) | (rangeAddrUp << 7) | (rangeAddrLow << 0);
473 
474  /* Run the test */
475  for (testStep = 0; testStep < 6; ++testStep)
476  {
477  mc->CONFIG0.U = configMarchUSequence[testStep] & 0x0000FFFF;
478  mc->CONFIG1.U = (configMarchUSequence[testStep] & 0xFFFF0000) >> 16;
479  mc->MCONTROL.U = 0x0209;
480  mc->MCONTROL.B.START = 0;
481 
482  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
483  IfxScuWdt_setSafetyEndinit(password);
484 
485  /* wait for the end of the fill operation */
486  IfxMtu_waitForMbistDone(IfxMtu_sramTable[mbistSel].mbistDelay, 4, mbistSel);
487  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, mc->MSTATUS.B.DONE != 0);
488 
489  while (!IfxMtu_isMbistDone(mbistSel))
490  {
491  __nop();
492  }
493 
494  /* Clear EndInit Again */
495  IfxScuWdt_clearSafetyEndinit(password);
496 
497  /* Check the Fail Status */
498  if (mc->MSTATUS.B.FAIL)
499  {
500  /* Test has failed, check if any un-correctable error */
501  if (mc->ECCD.B.UERR)
502  {
503  /* Read Error tracking register and return saying test failed */
504  *errorAddr = mc->ETRR[0].U;
505  retVal = 1U;
506  break;
507  }
508  }
509  }
510 
511  /* Disable Memory Controller */
512  IfxMtu_disableMbistShell(mbistSel);
513 
514  /* for auto-init memories: wait for the end of the clear operation */
515  while (IfxMtu_isAutoInitRunning(mbistSel))
516  {}
517 
518  /* Restore the endinit state */
519  if (isEndInitEnabled == 1)
520  {
521  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
522  IfxScuWdt_setSafetyEndinit(password);
523  }
524 
525  return retVal;
526 }
527 
528 
529 uint8 IfxMtu_runNonDestructiveInversionTest(IfxMtu_MbistSel mbistSel, uint8 rangeSel, uint8 rangeAddrUp, uint8 rangeAddrLow, uint16 *errorAddr)
530 {
531  /* Select MBIST Memory Controller:
532  * Ifx_MC is a type describing structure of MBIST Memory Controller
533  * registers defined in IfxMc_regdef.h file - MC object */
534  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
535  uint16 password = 0;
536  uint8 retVal = 0U;
537  uint8 isEndInitEnabled = 0;
538  password = IfxScuWdt_getSafetyWatchdogPassword();
539 
540  /* Check if the Endinit is cleared by application. If not, then handle it internally inside teh function.*/
541  if (IfxScuWdt_getSafetyWatchdogEndInit() == 1U)
542  {
543  /* Clear EndInit */
544  IfxScuWdt_clearSafetyEndinit(password);
545  isEndInitEnabled = 1;
546  }
547 
548  /* Enable MBIST Memory Controller */
549  IfxMtu_enableMbistShell(mbistSel);
550 
551  /* for auto-init memories: wait for the end of the clear operation */
552  while (IfxMtu_isAutoInitRunning(mbistSel))
553  {}
554 
555  /* Configure Non-destructive Inversion test */
556  mc->CONFIG0.U = 0x4005; //NUMACCS=4, ACCSTYPE=5
557  mc->CONFIG1.U = 0x5000; //AG_MOD=5
558  /* Set the range register */
559  mc->RANGE.U = (rangeSel << 15) | (rangeAddrUp << 7) | (rangeAddrLow << 0);
560  /* Run the tests */
561  mc->MCONTROL.U = 0xF201;
562  mc->MCONTROL.B.START = 0;
563  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
564  IfxScuWdt_setSafetyEndinit(password);
565 
566  /* wait for the end of the fill operation */
567  IfxMtu_waitForMbistDone(IfxMtu_sramTable[mbistSel].mbistDelay, 4, mbistSel);
568  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, mc->MSTATUS.B.DONE != 0);
569 
570  while (!IfxMtu_isMbistDone(mbistSel))
571  {
572  __nop();
573  }
574 
575  /* Clear EndInit Again */
576  IfxScuWdt_clearSafetyEndinit(password);
577 
578  /* Check the Fail Status */
579  if (mc->MSTATUS.B.FAIL)
580  {
581  /* Test has failed, check if any un-correctable error */
582  if (mc->ECCD.B.UERR)
583  {
584  /* Read the Error tracking register and return saying test failed */
585  *errorAddr = mc->ETRR[0].U;
586  retVal = 1U;
587  }
588  }
589 
590  /* Disable Memory Controller */
591  IfxMtu_disableMbistShell(mbistSel);
592 
593  /* for auto-init memories: wait for the end of the clear operation */
594  while (IfxMtu_isAutoInitRunning(mbistSel))
595  {}
596 
597  /* Restore the endinit state */
598  if (isEndInitEnabled == 1)
599  {
600  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
601  IfxScuWdt_setSafetyEndinit(password);
602  }
603 
604  return retVal;
605 }
606 
607 
608 static void IfxMtu_waitForMbistDone(uint32 towerDepth, uint8 numInstructions, IfxMtu_MbistSel mbistSel)
609 {
610  uint32 waitFact = (SCU_CCUCON0.B.SPBDIV / SCU_CCUCON0.B.SRIDIV) * numInstructions;
611  volatile uint32 waitTime;
612 
613  switch (mbistSel)
614  {
615  case IfxMtu_MbistSel_gtmFifo:
616  case IfxMtu_MbistSel_gtmMcs0:
617  case IfxMtu_MbistSel_gtmMcs1:
618  case IfxMtu_MbistSel_gtmDpll1a:
619  case IfxMtu_MbistSel_gtmDpll1b:
620  case IfxMtu_MbistSel_gtmDpll2:
621  waitFact = waitFact * SCU_CCUCON1.B.GTMDIV;
622  break;
623  case IfxMtu_MbistSel_ethermac:
624  waitFact = waitFact * SCU_CCUCON1.B.GTMDIV;
625  break;
626 
627  case IfxMtu_MbistSel_mcan:
628  case IfxMtu_MbistSel_psi5:
629  waitFact = waitFact * SCU_CCUCON0.B.BAUD1DIV;
630 
631  break;
632 
633  case IfxMtu_MbistSel_erayObf:
634  case IfxMtu_MbistSel_erayIbfTbf:
635  waitFact = (IfxScuCcu_getSriFrequency() / IfxScuCcu_getPll2ErayFrequency()) * numInstructions;
636  break;
637 
638  case IfxMtu_MbistSel_erayMbf:
639  waitFact = (IfxScuCcu_getSriFrequency() / IfxScuCcu_getPll2ErayFrequency()) * numInstructions * 4;
640  break;
641 
642  case IfxMtu_MbistSel_emem0:
643  case IfxMtu_MbistSel_emem1:
644  case IfxMtu_MbistSel_emem2:
645  case IfxMtu_MbistSel_emem3:
646  case IfxMtu_MbistSel_emem4:
647  case IfxMtu_MbistSel_emem5:
648  case IfxMtu_MbistSel_emem6:
649  case IfxMtu_MbistSel_emem7:
650  case IfxMtu_MbistSel_emem8:
651  case IfxMtu_MbistSel_emem9:
652  case IfxMtu_MbistSel_emem10:
653  case IfxMtu_MbistSel_emem11:
654  case IfxMtu_MbistSel_emem12:
655  case IfxMtu_MbistSel_emem13:
656  case IfxMtu_MbistSel_emem14:
657  case IfxMtu_MbistSel_emem15:
658  case IfxMtu_MbistSel_cifJpeg1_4:
659  case IfxMtu_MbistSel_cifJpeg3:
660  case IfxMtu_MbistSel_cifCif:
661  waitFact = waitFact * SCU_CCUCON2.B.BBBDIV;
662  break;
663  default:
664  break;
665  }
666 
667  if (numInstructions == 4)
668  {
669  waitTime = (towerDepth * waitFact) + 30;
670  }
671  else
672  {
673  waitTime = ((towerDepth / 4) * waitFact) + 30;
674  }
675 
676  waitTime = waitTime / 3;
677 
678  while (waitTime--)
679  {
680  __nop();
681  }
682 }
683 
684 
685 void IfxMtu_writeSramAddress(IfxMtu_MbistSel mbistSel, uint16 sramAddress)
686 {
687  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
688  uint8 isEndInitEnabled = 0;
689  uint16 password = 0;
690  password = IfxScuWdt_getSafetyWatchdogPassword();
691 
692  /* Check if the Endinit is cleared by application. If not, then handle it internally inside teh function.*/
693  if (IfxScuWdt_getSafetyWatchdogEndInit() == 1U)
694  {
695  /* Clear EndInit */
696  IfxScuWdt_clearSafetyEndinit(password);
697  isEndInitEnabled = 1;
698  }
699 
700  /* configure MBIST for single write opeation */
701  uint16 mcontrolMask = 0x4000; /* set USERED flag */
702  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DIR_OFF);
703  mc->CONFIG0.U = (1 << IFX_MC_CONFIG0_NUMACCS_OFF) | (0 << IFX_MC_CONFIG0_ACCSTYPE_OFF); /* 1 write access */
704  mc->CONFIG1.U = 0; /* ensure that linear scrambling is used */
705 
706  /* Set the address to be written (RAEN = 0) */
707  mc->RANGE.U = sramAddress;
708 
709  /* Start operation */
710  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DIR_OFF) | (1 << IFX_MC_MCONTROL_START_OFF);
711  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DIR_OFF);
712 
713  if (isEndInitEnabled == 1)
714  {
715  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
716  IfxScuWdt_setSafetyEndinit(password);
717  }
718 
719  /* Wait for the end of the operation */
720  IfxMtu_waitForMbistDone(IfxMtu_sramTable[mbistSel].mbistDelay, 1, mbistSel);
721  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, mc->MSTATUS.B.DONE != 0);
722 
723  while (!IfxMtu_isMbistDone(mbistSel))
724  {
725  __nop();
726  }
727 }