iLLD_TC29x  1.0
IfxEbu.h File Reference

EBU basic functionality. More...

#include "_Impl/IfxEbu_cfg.h"
#include "IfxEbu_reg.h"

Go to the source code of this file.

Data Structures

struct  IfxEbu_MemoryRegionConfig
 
struct  IfxEbu_ModuleConfig
 
struct  IfxEbu_ReadAccessParameter
 
struct  IfxEbu_ReadConfig
 
struct  IfxEbu_SDRAMControlConfig
 
struct  IfxEbu_SDRAMModConfig
 
struct  IfxEbu_SDRAMRefreshConfig
 
struct  IfxEbu_WriteAccessParameter
 
struct  IfxEbu_WriteConfig
 

Enumerations

enum  IfxEbu_ChipSelect {
  IfxEbu_ChipSelect_0,
  IfxEbu_ChipSelect_1,
  IfxEbu_ChipSelect_2
}
 
enum  IfxEbu_ExternalClockRatio {
  IfxEbu_ExternalClockRatio_1,
  IfxEbu_ExternalClockRatio_2,
  IfxEbu_ExternalClockRatio_3,
  IfxEbu_ExternalClockRatio_4,
  IfxEbu_ExternalClockRatio_6,
  IfxEbu_ExternalClockRatio_8
}
 
enum  IfxEbu_AlternateSegmentCompare {
  IfxEbu_AlternateSegmentCompare_disabled = 0,
  IfxEbu_AlternateSegmentCompare_enabled = 1
}
 
enum  IfxEbu_ArbitrationSignalSynchronization {
  IfxEbu_ArbitrationSignalSynchronization_synchronous = 0,
  IfxEbu_ArbitrationSignalSynchronization_asynchronous = 1
}
 
enum  IfxEbu_ByteControl {
  IfxEbu_ByteControl_byteControlFollowingChipSelect = 0,
  IfxEbu_ByteControl_bytecontrolFollowingControlSignal = 1,
  IfxEbu_ByteControl_byteControlFollowingWriteEnable = 2,
  IfxEbu_ByteControl_sdramAccessDQM = 3
}
 
enum  IfxEbu_ByteControlEnable {
  IfxEbu_ByteControlEnable_byteControlOff = 0,
  IfxEbu_ByteControlEnable_byteControl8Bit = 1,
  IfxEbu_ByteControlEnable_byteControl16Bit = 2,
  IfxEbu_ByteControlEnable_byteControl32Bit = 3
}
 
enum  IfxEbu_CASLatency {
  IfxEbu_CASLatency_Latency2 = 2,
  IfxEbu_CASLatency_Latency3 = 3
}
 
enum  IfxEbu_ClockDivideRatio {
  IfxEbu_ClockDivideRatio_0 = 0,
  IfxEbu_ClockDivideRatio_1,
  IfxEbu_ClockDivideRatio_2,
  IfxEbu_ClockDivideRatio_3
}
 
enum  IfxEbu_ClockSource {
  IfxEbu_ClockSource_asynchronous = 0,
  IfxEbu_ClockSource_synchronous = 1
}
 
enum  IfxEbu_ColumnAddressWidth {
  IfxEbu_ColumnAddressWidth_1 = 1,
  IfxEbu_ColumnAddressWidth_2 = 2,
  IfxEbu_ColumnAddressWidth_3 = 3
}
 
enum  IfxEbu_DelayOnPowerDownExit {
  IfxEbu_DelayOnPowerDownExit_0,
  IfxEbu_DelayOnPowerDownExit_1,
  IfxEbu_DelayOnPowerDownExit_2,
  IfxEbu_DelayOnPowerDownExit_3,
  IfxEbu_DelayOnPowerDownExit_4,
  IfxEbu_DelayOnPowerDownExit_5,
  IfxEbu_DelayOnPowerDownExit_6,
  IfxEbu_DelayOnPowerDownExit_7
}
 
enum  IfxEbu_DeviceType {
  IfxEbu_DeviceType_muxedAsynchronousType = 0,
  IfxEbu_DeviceType_muxedBurstType = 1,
  IfxEbu_DeviceType_nandFlash = 2,
  IfxEbu_DeviceType_muxedCellularRam = 3,
  IfxEbu_DeviceType_demuxedAsynchronousType = 4,
  IfxEbu_DeviceType_demuxedBurstType = 5,
  IfxEbu_DeviceType_demuxedPageMode = 6,
  IfxEbu_DeviceType_demuxedCellularRam = 7,
  IfxEbu_DeviceType_sdram = 8
}
 
enum  IfxEbu_ExtendedData {
  IfxEbu_ExtendedData_0,
  IfxEbu_ExtendedData_1,
  IfxEbu_ExtendedData_2,
  IfxEbu_ExtendedData_3
}
 
enum  IfxEbu_ExtendedOperationBankSelect {
  IfxEbu_ExtendedOperationBankSelect_0,
  IfxEbu_ExtendedOperationBankSelect_1,
  IfxEbu_ExtendedOperationBankSelect_2,
  IfxEbu_ExtendedOperationBankSelect_3
}
 
enum  IfxEbu_ExtendedRefresh {
  IfxEbu_ExtendedRefresh_0,
  IfxEbu_ExtendedRefresh_1,
  IfxEbu_ExtendedRefresh_2,
  IfxEbu_ExtendedRefresh_3
}
 
enum  IfxEbu_ExternalBusMode {
  IfxEbu_ExternalBusMode_noBus = 0,
  IfxEbu_ExternalBusMode_arbiter = 1,
  IfxEbu_ExternalBusMode_participant = 2,
  IfxEbu_ExternalBusMode_soleMaster = 3
}
 
enum  IfxEbu_ExternalDeviceInterface {
  IfxEbu_ExternalDeviceInterface_8bitMultiplexed = 0,
  IfxEbu_ExternalDeviceInterface_16bitMultiplexed = 1,
  IfxEbu_ExternalDeviceInterface_twin16bitMultiplexed = 2,
  IfxEbu_ExternalDeviceInterface_32bitMultiplexed = 3
}
 
enum  IfxEbu_ExternalMemoryWriteProtect {
  IfxEbu_ExternalMemoryWriteProtect_disabled = 0,
  IfxEbu_ExternalMemoryWriteProtect_enabled = 1
}
 
enum  IfxEbu_MaskForBankTag {
  IfxEbu_MaskForBankTag_1 = 1,
  IfxEbu_MaskForBankTag_2 = 2,
  IfxEbu_MaskForBankTag_3 = 3,
  IfxEbu_MaskForBankTag_4 = 4,
  IfxEbu_MaskForBankTag_5 = 5,
  IfxEbu_MaskForBankTag_6 = 6
}
 
enum  IfxEbu_MemoryRegionMask {
  IfxEbu_MemoryRegionMask_0,
  IfxEbu_MemoryRegionMask_1,
  IfxEbu_MemoryRegionMask_2,
  IfxEbu_MemoryRegionMask_3,
  IfxEbu_MemoryRegionMask_4,
  IfxEbu_MemoryRegionMask_5,
  IfxEbu_MemoryRegionMask_6,
  IfxEbu_MemoryRegionMask_7,
  IfxEbu_MemoryRegionMask_8,
  IfxEbu_MemoryRegionMask_9,
  IfxEbu_MemoryRegionMask_10,
  IfxEbu_MemoryRegionMask_11,
  IfxEbu_MemoryRegionMask_12,
  IfxEbu_MemoryRegionMask_13,
  IfxEbu_MemoryRegionMask_14,
  IfxEbu_MemoryRegionMask_15
}
 
enum  IfxEbu_ModeRegisterSetupTime {
  IfxEbu_ModeRegisterSetupTime_0,
  IfxEbu_ModeRegisterSetupTime_1,
  IfxEbu_ModeRegisterSetupTime_2,
  IfxEbu_ModeRegisterSetupTime_3
}
 
enum  IfxEbu_PowerSaveMode {
  IfxEbu_PowerSaveMode_0,
  IfxEbu_PowerSaveMode_1,
  IfxEbu_PowerSaveMode_2,
  IfxEbu_PowerSaveMode_3
}
 
enum  IfxEbu_RefreshCommands {
  IfxEbu_RefreshCommands_0,
  IfxEbu_RefreshCommands_1,
  IfxEbu_RefreshCommands_2,
  IfxEbu_RefreshCommands_3,
  IfxEbu_RefreshCommands_4,
  IfxEbu_RefreshCommands_5,
  IfxEbu_RefreshCommands_6,
  IfxEbu_RefreshCommands_7
}
 
enum  IfxEbu_RowPrechargeTime {
  IfxEbu_RowPrechargeTime_0,
  IfxEbu_RowPrechargeTime_1,
  IfxEbu_RowPrechargeTime_2,
  IfxEbu_RowPrechargeTime_3
}
 
enum  IfxEbu_RowToColumnDelay {
  IfxEbu_RowToColumnDelay_0,
  IfxEbu_RowToColumnDelay_1,
  IfxEbu_RowToColumnDelay_2,
  IfxEbu_RowToColumnDelay_3
}
 
enum  IfxEbu_SDRAMBurstLength {
  IfxEbu_SDRAMBurstLength_1 = 0,
  IfxEbu_SDRAMBurstLength_2 = 1,
  IfxEbu_SDRAMBurstLength_4 = 2,
  IfxEbu_SDRAMBurstLength_8 = 3,
  IfxEbu_SDRAMBurstLength_16 = 4
}
 
enum  IfxEbu_SynchronousBurstBuffer {
  IfxEbu_SynchronousBurstBuffer_bufferLength = 0,
  IfxEbu_SynchronousBurstBuffer_continuous = 1
}
 
enum  IfxEbu_SynchronousBurstLength {
  IfxEbu_SynchronousBurstLength_1 = 0,
  IfxEbu_SynchronousBurstLength_2 = 1,
  IfxEbu_SynchronousBurstLength_4 = 2,
  IfxEbu_SynchronousBurstLength_8 = 3
}
 
enum  IfxEbu_WaitControl {
  IfxEbu_WaitControl_off = 0,
  IfxEbu_WaitControl_asynchronous = 1,
  IfxEbu_WaitControl_synchronous = 2
}
 

Functions

IFX_EXTERN void IfxEbu_setExternalClockRatio (Ifx_EBU *ebu, IfxEbu_ExternalClockRatio ratio)
 Configures the EBU Clock Divider. More...
 
IFX_EXTERN void IfxEbu_setByteControlEnable (Ifx_EBU *ebu, IfxEbu_ByteControlEnable byteControlEnable)
 configures the byte control enable in the USERCON register More...
 

Detailed Description

EBU basic functionality.

Version
iLLD_1_0_0_11_0
                            IMPORTANT NOTICE

Infineon Technologies AG (Infineon) is supplying this file for use exclusively with Infineon's microcontroller products. This file can be freely distributed within development tools that are supporting such microcontroller products.

THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

Definition in file IfxEbu.h.


Data Structure Documentation

struct IfxEbu_MemoryRegionConfig

Definition at line 306 of file IfxEbu.h.

Data Fields
IfxEbu_MemoryRegionMask addressMask
uint8 alternateSegment
boolean alternateSegmentEnabled
uint32 baseAddress
boolean combinedChipSelect
boolean regionEnabled
boolean writeProtection
struct IfxEbu_ModuleConfig

Definition at line 317 of file IfxEbu.h.

Data Fields
boolean aleMode when '0' output is ADV, when '1' output is ALE
IfxEbu_ExternalBusMode arbMode Arbitration mode of External Bus.
IfxEbu_ArbitrationSignalSynchronization arbSignalSynchronization Arbitration signal Synchronization mode.
boolean clockComb Both BFlash and SDRAM share the same clock out.
uint8 lockTimeout Value for preloaded for arbitration lock.
boolean sdramTri when '0' SDRAM control Signals are driven by EBU, when '1' SDRAM control signals are tristated
struct IfxEbu_ReadAccessParameter

Definition at line 327 of file IfxEbu.h.

Data Fields
uint8 addressCycle BUSRAP.ADDRC Number of Clock Phase for Address.
uint8 addressHold BUSRAP.AHOLDC Number of Cycles for Address Hold Phase.
uint8 commandDelay BUSRAP.CMDDELAY Number of Command Delay Phase Clock Cycles.
uint8 dataHold BUSRAP.DATAC Data Hold Cycles for Read.
IfxEbu_ExtendedData extendedData BUSRAP.EXTDATA Determines the Clock Cycles after which the data is put out.
uint8 externalClock BUSRAP.EXTCLOCK Determines the Clock Ratio between EBU_CLC and BFCLK or SDCLK.
uint8 recoveryAccess BUSRAP.RDRECOVC Recovery cycles at end of Read Access.
uint8 recoveryRegion BUSRAP.RDDTACS Recovery cycles between different regions.
uint8 waitState BUSRAP.WAITRDC Number of Wait States for Read.
struct IfxEbu_ReadConfig

Definition at line 340 of file IfxEbu.h.

Data Fields
boolean burstFlashClockFeedback BUSRCON.FDBKEN if '1' Feedback clock is used for resynchronizing the contol and data coming in.
boolean burstFlashClockMode BUSRCON.BFCMSEL if '1' Clock is disabled between Access.
IfxEbu_SynchronousBurstLength burstLength BUSRCON.FETBLEN Defines maximum number of Burst Data.
uint8 byteControl BUSRCON.BCGEN selects the timing mode of byte control.
IfxEbu_ExternalDeviceInterface deviceInterface BUSRCON.PORTW Selects the device Addressing mode (16bit, 32bit, 2*16bit)
IfxEbu_DeviceType deviceType BUSRCON.AGEN Device selection for Read.
boolean earlyBurst BUSRCON.EBSE if '1' ADV is not delayed.
boolean earlyChipSelect BUSRCON.ECSE if '1' CS is not delayed.
boolean polarityWait BUSRCON.WAITINV if '1' the polarity is reversed.
boolean synchronousBurstBuffer BUSRCON.FBBMSEL The data is either continuous or depends on FETLBEN.
IfxEbu_WaitControl waitControl BUSRCON.WAIT, External Wait Control.
struct IfxEbu_SDRAMControlConfig

Definition at line 355 of file IfxEbu.h.

Data Fields
boolean clockModeSelect if '0' clock is running continuously, if '1' clock is disabled between access
IfxEbu_ColumnAddressWidth columnAddressWidth Number of Address bits from 0 used for Column Addressing.
boolean disableClockOutput if '0' Clock is enabled
uint8 initializationRefreshCommand Number of Refresh cycles issued during Initialization.
IfxEbu_MaskForBankTag maskForBankTag SRI address bits used to determine Bank Address.
IfxEbu_ModeRegisterSetupTime modeRegSetupTime Number of NOP commands after a mode register set command.
IfxEbu_PowerSaveMode powerSaveMode Power save mode used for Gated Clock mode.
uint8 refreshCycleTime Number of NOP cycles following Refresh cycle.
IfxEbu_RowPrechargeTime rowPrechargeTime Number of NOP commands inserted after Precharge.
IfxEbu_RowToColumnDelay rowToColumnDelay Number of NOP commands between Row address and Column address.
uint8 rowToPrechargeDelay Number of clock cycles between Row Activate command and a Precharge command.
struct IfxEbu_SDRAMModConfig

Definition at line 370 of file IfxEbu.h.

Data Fields
IfxEbu_SDRAMBurstLength burstLength Number of location that can be accessed in a single command.
IfxEbu_CASLatency casLatency Number of Clock cycles between the availability of data an Read Access.
boolean coldStart If '1' is written the SDRAM device register will be updated.
IfxEbu_ExtendedOperationBankSelect extendedBankSelect Value to be written to bank select pins of a mobile SDRAM.
uint16 extendedOperationMode Value to be written to the extended mode register of a mobile SDRAM device.
uint8 opmode
struct IfxEbu_SDRAMRefreshConfig

Definition at line 380 of file IfxEbu.h.

Data Fields
boolean automaticSelfRefresh If '1' Automatic Self Refresh command will be issued for Entry and Exit.
boolean autoRefresh If '1' Auto Refresh will be enabled before Self Refresh Exit.
IfxEbu_DelayOnPowerDownExit delayOnPowerDownExit Number of Nops after SDRAM Controller exits Power down before an active command is active.
IfxEbu_ExtendedRefresh extendedRefresh Used to Increase the Range of RefreshC field from 6 bits to 8 bits.
IfxEbu_RefreshCommands refreshCommands The Number of additional Refresh commands issued to SDRAM each time a refresh is due.
uint8 refreshPeriod Number of clock Cycles between Refresh.
boolean selfRefreshEntry If '1' Self Refresh Entry command is issued.
boolean selfRefreshExit If '1' Self Refresh Exit commands are issued.
uint8 selfRefreshExitDelay Number of Nops inserted after Self Refresh Command.
struct IfxEbu_WriteAccessParameter

Definition at line 393 of file IfxEbu.h.

Data Fields
uint8 addressCycle BUSWAP.ADDRC Number of Clock Phase for Address.
uint8 addressHold BUSWAP.AHOLDC Number of Cycles for Address Hold Phase.
uint8 commandDelay BUSWAP.CMDDELAY Number of Command Delay Phase Clock Cycles.
uint8 dataHold BUSWAP.DATAC Data Hold Cycles for WRITE.
IfxEbu_ExtendedData extendedData BUSWAP.EXTDATA Determines the Clock Cycles after which the data is put out.
uint8 externalClock BUSWAP.EXTCLOCK Determines the Clock Ratio between EBU_CLC and BFCLK or SDCLK.
uint8 recoveryAccess BUSWAP.WRRECOVC Recovery cycles at end of Write Access.
uint8 recoveryRegion BUSWAP.WRDTACS Recovery cycles between different regions.
uint8 waitState BUSRAP.WAITWRC Number of Wait States for Write.
struct IfxEbu_WriteConfig

Definition at line 406 of file IfxEbu.h.

Data Fields
IfxEbu_SynchronousBurstLength burstLength BUSWCON.FETBLEN Defines maximum number of Burst Data.
uint8 byteControl BUSWCON.BCGEN selects the timing mode of byte control.
IfxEbu_ExternalDeviceInterface deviceInterface BUSWCON.PORTW Selects the device Addressing mode (16bit, 32bit, 2*16bit)
IfxEbu_DeviceType deviceType BUSWCON.AGEN Device selection for Read.
boolean earlyBurst BUSWCON.EBSE if '1' ADV is not delayed.
boolean earlyChipSelect BUSWCON.ECSE if '1' CS is not delayed.
boolean polarityWait BUSWCON.WAITINV if '1' the polarity is reversed.
boolean synchronousBurstBuffer BUSWCON.FBBMSEL The data is either continuous or depends on FETLBEN.
IfxEbu_WaitControl waitControl BUSWCON.WAIT, External Wait Control.

Enumeration Type Documentation

Enumerator
IfxEbu_AlternateSegmentCompare_disabled 

Alternate Segment is never Compared with SRI Bus.

IfxEbu_AlternateSegmentCompare_enabled 

Alternate Segment Address is always compared.

Definition at line 67 of file IfxEbu.h.

Enumerator
IfxEbu_ArbitrationSignalSynchronization_synchronous 

Arbitration Signals are Synchronous.

IfxEbu_ArbitrationSignalSynchronization_asynchronous 

Arbitration inputs are Asynchronous.

Definition at line 73 of file IfxEbu.h.

Enumerator
IfxEbu_ByteControl_byteControlFollowingChipSelect 
IfxEbu_ByteControl_bytecontrolFollowingControlSignal 
IfxEbu_ByteControl_byteControlFollowingWriteEnable 
IfxEbu_ByteControl_sdramAccessDQM 

Definition at line 79 of file IfxEbu.h.

Enumerator
IfxEbu_ByteControlEnable_byteControlOff 

Byte control off. Pins available for address or GPIO as set by Ports logic.

IfxEbu_ByteControlEnable_byteControl8Bit 

8 bit byte control. Byte control 0 only. A(22:20) available for address or GPIO as set by Ports logic

IfxEbu_ByteControlEnable_byteControl16Bit 

16 bit byte control. BC(1:0) available. A(21:20) available for address or GPIO as set by Ports logic

IfxEbu_ByteControlEnable_byteControl32Bit 

32 bit byte control. BC(3:0) available

Definition at line 87 of file IfxEbu.h.

Enumerator
IfxEbu_CASLatency_Latency2 

CAS Latency 2 between Read Command and availability of Data.

IfxEbu_CASLatency_Latency3 

CAS Latency 3 between Read Access and availability of Data.

Definition at line 100 of file IfxEbu.h.

Enumerator
IfxEbu_ClockDivideRatio_0 

EBU Clock divide Ratio.

IfxEbu_ClockDivideRatio_1 

EBU Clock divide Ratio.

IfxEbu_ClockDivideRatio_2 

EBU Clock divide Ratio.

IfxEbu_ClockDivideRatio_3 

EBU Clock divide Ratio.

Definition at line 106 of file IfxEbu.h.

Enumerator
IfxEbu_ClockSource_asynchronous 

EBU input clock is in Asynchronous mode;.

IfxEbu_ClockSource_synchronous 

EBU Input Clock Source is from PLL;.

Definition at line 114 of file IfxEbu.h.

Enumerator
IfxEbu_ColumnAddressWidth_1 

Asri[8:0] for 16bit 512bytes and Asri[9:0] for 32bit 1024bytes.

IfxEbu_ColumnAddressWidth_2 

Asri[9:0] for 16bit 1024 bytes and Asri[10:0] for 32bit 2048 bytes.

IfxEbu_ColumnAddressWidth_3 

Asri[10:0] for 16bit 1024 bytes and Asri[11:0] for 32bit 4096 bytes.

Definition at line 120 of file IfxEbu.h.

Enumerator
IfxEbu_DelayOnPowerDownExit_0 

Number of Nops after SDRAM controller exits power down.

IfxEbu_DelayOnPowerDownExit_1 

Number of Nops after SDRAM controller exits power down.

IfxEbu_DelayOnPowerDownExit_2 

Number of Nops after SDRAM controller exits power down.

IfxEbu_DelayOnPowerDownExit_3 

Number of Nops after SDRAM controller exits power down.

IfxEbu_DelayOnPowerDownExit_4 

Number of Nops after SDRAM controller exits power down.

IfxEbu_DelayOnPowerDownExit_5 

Number of Nops after SDRAM controller exits power down.

IfxEbu_DelayOnPowerDownExit_6 

Number of Nops after SDRAM controller exits power down.

IfxEbu_DelayOnPowerDownExit_7 

Number of Nops after SDRAM controller exits power down.

Definition at line 127 of file IfxEbu.h.

Enumerator
IfxEbu_DeviceType_muxedAsynchronousType 

External Device is a Muxed Asynchronous Type Device.

IfxEbu_DeviceType_muxedBurstType 

External Device is a Muxed Burst Type.

IfxEbu_DeviceType_nandFlash 

External Device is a Nand Flash device.

IfxEbu_DeviceType_muxedCellularRam 

External Device is a Muxed Cellular Ram Device.

IfxEbu_DeviceType_demuxedAsynchronousType 

External Device is a Demuxed Asynchronous Type device.

IfxEbu_DeviceType_demuxedBurstType 

External device is a Demuxed Burst Type device.

IfxEbu_DeviceType_demuxedPageMode 

External device is a Demuxed Page Mode Device.

IfxEbu_DeviceType_demuxedCellularRam 

External device is a Demuxed Cellular Ram Device.

IfxEbu_DeviceType_sdram 

External Device is a SDRAM Device.

Definition at line 139 of file IfxEbu.h.

Enumerator
IfxEbu_ExtendedData_0 

Data is output every 2*str(x) Clock Cycle(s)

IfxEbu_ExtendedData_1 

Data is output every 2*str(x) Clock Cycle(s)

IfxEbu_ExtendedData_2 

Data is output every 2*str(x) Clock Cycle(s)

IfxEbu_ExtendedData_3 

Data is output every 2*str(x) Clock Cycle(s)

Definition at line 152 of file IfxEbu.h.

Enumerator
IfxEbu_ExtendedOperationBankSelect_0 

Value written to Bank Select Pins of Mobile SDRAM.

IfxEbu_ExtendedOperationBankSelect_1 

Value written to Bank Select Pins of Mobile SDRAM.

IfxEbu_ExtendedOperationBankSelect_2 

Value written to Bank Select Pins of Mobile SDRAM.

IfxEbu_ExtendedOperationBankSelect_3 

Value written to Bank Select Pins of Mobile SDRAM.

Definition at line 160 of file IfxEbu.h.

Enumerator
IfxEbu_ExtendedRefresh_0 
IfxEbu_ExtendedRefresh_1 
IfxEbu_ExtendedRefresh_2 
IfxEbu_ExtendedRefresh_3 

Definition at line 168 of file IfxEbu.h.

Enumerator
IfxEbu_ExternalBusMode_noBus 

EBU is in NoBus Mode.

IfxEbu_ExternalBusMode_arbiter 

EBU is in Arbiter mode;.

IfxEbu_ExternalBusMode_participant 

EBU is in Participant Mode;.

IfxEbu_ExternalBusMode_soleMaster 

EBU is in Sole Master Mode.

Definition at line 176 of file IfxEbu.h.

Enumerator
IfxEbu_ExternalDeviceInterface_8bitMultiplexed 

External Device is an 8 Bit Device.

IfxEbu_ExternalDeviceInterface_16bitMultiplexed 

External evice is an 16 bit Multiplexed.

IfxEbu_ExternalDeviceInterface_twin16bitMultiplexed 

Two External 16 bit Multiplexed Devices are used.

IfxEbu_ExternalDeviceInterface_32bitMultiplexed 

External device is an 32 bit Multiplexed device.

Definition at line 184 of file IfxEbu.h.

Enumerator
IfxEbu_ExternalMemoryWriteProtect_disabled 

External memory is writable.

IfxEbu_ExternalMemoryWriteProtect_enabled 

External Memory is write protected.

Definition at line 192 of file IfxEbu.h.

Enumerator
IfxEbu_MaskForBankTag_1 

Asri[21 to 20].

IfxEbu_MaskForBankTag_2 

Asri[22 to 21].

IfxEbu_MaskForBankTag_3 

Asri[23 to 22].

IfxEbu_MaskForBankTag_4 

Asri[24 to 23].

IfxEbu_MaskForBankTag_5 

Asri[25 to 24].

IfxEbu_MaskForBankTag_6 

Asri[26 to 25].

Definition at line 198 of file IfxEbu.h.

Enumerator
IfxEbu_MemoryRegionMask_0 

Mask1.

IfxEbu_MemoryRegionMask_1 

Mask2.

IfxEbu_MemoryRegionMask_2 

Mask3.

IfxEbu_MemoryRegionMask_3 

Mask4.

IfxEbu_MemoryRegionMask_4 

Mask5.

IfxEbu_MemoryRegionMask_5 

Mask6.

IfxEbu_MemoryRegionMask_6 

Mask7.

IfxEbu_MemoryRegionMask_7 

Mask8.

IfxEbu_MemoryRegionMask_8 

Mask9.

IfxEbu_MemoryRegionMask_9 

Mask10.

IfxEbu_MemoryRegionMask_10 

Mask11.

IfxEbu_MemoryRegionMask_11 

Mask12.

IfxEbu_MemoryRegionMask_12 

Mask13.

IfxEbu_MemoryRegionMask_13 

Mask14.

IfxEbu_MemoryRegionMask_14 

Mask15.

IfxEbu_MemoryRegionMask_15 

Mask16.

Definition at line 208 of file IfxEbu.h.

Enumerator
IfxEbu_ModeRegisterSetupTime_0 

Number of Nop Cycles after a Mode Register Set Command (Crsc + 1) Nop cycles.

IfxEbu_ModeRegisterSetupTime_1 

Number of Nop Cycles after a Mode Register Set Command (Crsc + 1) Nop cycles.

IfxEbu_ModeRegisterSetupTime_2 

Number of Nop Cycles after a Mode Register Set Command (Crsc + 1) Nop cycles.

IfxEbu_ModeRegisterSetupTime_3 

Number of Nop Cycles after a Mode Register Set Command (Crsc + 1) Nop cycles.

Definition at line 228 of file IfxEbu.h.

Enumerator
IfxEbu_PowerSaveMode_0 

Power Save mode used for clock gate mode.

IfxEbu_PowerSaveMode_1 

Power Save mode used for clock gate mode.

IfxEbu_PowerSaveMode_2 

Power Save mode used for clock gate mode.

IfxEbu_PowerSaveMode_3 

Power Save mode used for clock gate mode.

Definition at line 236 of file IfxEbu.h.

Enumerator
IfxEbu_RefreshCommands_0 
IfxEbu_RefreshCommands_1 
IfxEbu_RefreshCommands_2 
IfxEbu_RefreshCommands_3 
IfxEbu_RefreshCommands_4 
IfxEbu_RefreshCommands_5 
IfxEbu_RefreshCommands_6 
IfxEbu_RefreshCommands_7 

Definition at line 244 of file IfxEbu.h.

Enumerator
IfxEbu_RowPrechargeTime_0 

Number of Nops inserted after Precharge command (Crp + 1) Nop Cycles.

IfxEbu_RowPrechargeTime_1 

Number of Nops inserted after Precharge command (Crp + 1) Nop Cycles.

IfxEbu_RowPrechargeTime_2 

Number of Nops inserted after Precharge command (Crp + 1) Nop Cycles.

IfxEbu_RowPrechargeTime_3 

Number of Nops inserted after Precharge command (Crp + 1) Nop Cycles.

Definition at line 256 of file IfxEbu.h.

Enumerator
IfxEbu_RowToColumnDelay_0 

Number of Nops between Row Address and Column Address (Crcd(value) + 1 Nop Cycle)

IfxEbu_RowToColumnDelay_1 

Number of Nops between Row Address and Column Address (Crcd(value) + 1 Nop Cycle)

IfxEbu_RowToColumnDelay_2 

Number of Nops between Row Address and Column Address (Crcd(value) + 1 Nop Cycle)

IfxEbu_RowToColumnDelay_3 

Number of Nops between Row Address and Column Address (Crcd(value) + 1 Nop Cycle)

Definition at line 264 of file IfxEbu.h.

Enumerator
IfxEbu_SDRAMBurstLength_1 

Burst Length 1.

IfxEbu_SDRAMBurstLength_2 

Burst Length 2.

IfxEbu_SDRAMBurstLength_4 

Burst Length 4.

IfxEbu_SDRAMBurstLength_8 

Burst Length 8.

IfxEbu_SDRAMBurstLength_16 

Burst Length 16.

Definition at line 272 of file IfxEbu.h.

Enumerator
IfxEbu_SynchronousBurstBuffer_bufferLength 

EBU Buffer length = IfxEbu_SynchronousBurstLength;.

IfxEbu_SynchronousBurstBuffer_continuous 

EBU External Data is Transferred in Single Burst;.

Definition at line 281 of file IfxEbu.h.

Enumerator
IfxEbu_SynchronousBurstLength_1 

EBU Burst Length is 1;.

IfxEbu_SynchronousBurstLength_2 

EBU Burst length is 2.

IfxEbu_SynchronousBurstLength_4 

EBU Burst Length is 4.

IfxEbu_SynchronousBurstLength_8 

EBU Burst Length is 8.

Definition at line 287 of file IfxEbu.h.

Enumerator
IfxEbu_WaitControl_off 

External Wait is off.

IfxEbu_WaitControl_asynchronous 

Asynchronous input for wait (Asynchronous Device) & Wait for Page load (Synchronous Device)

IfxEbu_WaitControl_synchronous 

Synchronous input for wait (Asynchronous Device) & wait for Page load (with Data) (Synchronous Device)

Definition at line 295 of file IfxEbu.h.