106 static uint32 IfxQspi_SpiMaster_dummyRxValue = 0;
110 static const uint32 IfxQspi_SpiMaster_dummyTxValue = ~0;
166 handle->
qspi->XXLCON.B.XDL = count - 1;
185 Ifx_QSPI *qspiSFR = handle->
qspi;
187 econ.U = qspiSFR->ECON[chHandle->
channelId % 8].U;
231 Ifx_QSPI *qspiSFR = handle->
qspi;
251 __ldmst(&qspiSFR->SSOC.U, (mask | (mask << 16)), (aol | oen));
258 chHandle->slso = slso->
pin;
259 chHandle->slsoActiveState = chConfig->base.mode.csActiveLevel;
261 if (chHandle->slso.port ==
NULL_PTR)
264 chHandle->deactivateSlso =
NULL_PTR;
268 if (!chConfig->base.mode.autoCS)
270 chHandle->activateSlso = &IfxQspi_SpiMaster_activateSlso;
271 chHandle->deactivateSlso = &IfxQspi_SpiMaster_deactivateSlso;
274 chHandle->deactivateSlso(chHandle);
280 chHandle->deactivateSlso =
NULL_PTR;
285 chHandle->dataWidth = chConfig->base.mode.dataWidth;
286 chHandle->base.txHandler = (
TxRxHandler) & IfxQspi_SpiMaster_write;
287 chHandle->base.rxHandler = (
TxRxHandler) & IfxQspi_SpiMaster_read;
291 Ifx_DMA *dmaSFR = &MODULE_DMA;
314 Ifx_QSPI *qspiSFR = config->
qspi;
316 Ifx_DMA *dmaSFR = &MODULE_DMA;
328 Ifx_QSPI_GLOBALCON globalcon;
340 globalcon.B.RESETS = 1;
341 qspiSFR->GLOBALCON.U = globalcon.U;
345 Ifx_QSPI_GLOBALCON1 globalcon1;
352 qspiSFR->GLOBALCON1.U = globalcon1.U;
382 handle->
qspi = qspiSFR;
527 Ifx_DMA *dmaSFR = &MODULE_DMA;
549 Ifx_DMA *dmaSFR = &MODULE_DMA;
551 Ifx_QSPI *qspiSFR = qspiHandle->
qspi;
603 Ifx_QSPI *qspiSFR = handle->
qspi;
607 Ifx_DMA *dmaSFR = &MODULE_DMA;
672 Ifx_QSPI *qspiSFR = handle->
qspi;
675 if (qspiSFR->STATUS.B.PT1F)
677 qspiSFR->FLAGSCLEAR.B.PT1C = 1;
678 ptEvent = qspiSFR->GLOBALCON1.B.PT1;
680 else if (qspiSFR->STATUS.B.PT2F)
682 qspiSFR->FLAGSCLEAR.B.PT2C = 1;
683 ptEvent = qspiSFR->GLOBALCON1.B.PT2;
708 Ifx_QSPI *qspiSFR = handle->
qspi;
711 if (qspiSFR->STATUS.B.USRF)
713 qspiSFR->FLAGSCLEAR.B.USRC = 1;
714 ptEvent = qspiSFR->GLOBALCON1.B.PT1;
739 chHandle->
bacon.B.BYTE = 1;
740 chHandle->
bacon.B.LAST = 0;
744 chHandle->
bacon.B.BYTE = 1;
745 chHandle->
bacon.B.LAST = 1;
752 while (dataLength > 0)
754 if (dataLength <= 16)
756 baconDL = dataLength;
757 chHandle->
bacon.B.LAST = 1;
769 chHandle->
bacon.B.DL = baconDL - 1;
770 *longFifoBuffer = chHandle->
bacon.U;
774 for (i = 0; i < baconDL / 4; i++)
776 *longFifoBuffer = *((
uint32 *)src);
785 *longFifoBuffer = *src;
788 *longFifoBuffer = *src | (*(src + 1) << 8);
791 *longFifoBuffer = *src | (*(src + 1) << 8) | (*(src + 2) << 16);
801 Ifx_QSPI *qspiSFR = handle->
qspi;
812 for (i = 0; i < count; ++i)
855 Ifx_QSPI *qspiSFR = handle->
qspi;
881 Ifx_DMA *dmaSFR = &MODULE_DMA;
883 Ifx_QSPI *qspiSFR = handle->
qspi;
915 dmaSFR->CH[txDmaChannelId].ADICR.B.SCBE =
TRUE;
924 dmaSFR->CH[txDmaChannelId].ADICR.B.SCBE =
FALSE;
957 dmaSFR->CH[rxDmaChannelId].ADICR.B.DCBE =
TRUE;
966 dmaSFR->CH[rxDmaChannelId].ADICR.B.DCBE =
FALSE;
1029 Ifx_QSPI *qspiSFR = handle->
qspi;
1057 boolean lastWrite = job->
remaining == 0;
1066 for (i = 0; i < count - 1; ++i)
1076 for (i = 0; i < count; ++i)
1161 Ifx_DMA *dmaSFR = &MODULE_DMA;
1163 Ifx_QSPI *qspiSFR = handle->
qspi;
1182 dmaSFR->CH[txDmaChannelId].ADICR.B.SCBE =
FALSE;
1206 dmaSFR->CH[rxDmaChannelId].ADICR.B.DCBE =
TRUE;
1215 dmaSFR->CH[rxDmaChannelId].ADICR.B.DCBE =
FALSE;
1233 chHandle->
bacon.B.BYTE = 1;
1238 chHandle->
bacon.B.LAST = 1;
1239 chHandle->
bacon.B.BYTE = 1;
1243 chHandle->
bacon.B.LAST = 1;
1244 chHandle->
bacon.B.BYTE = 1;
1245 chHandle->
bacon.B.DL = 0;
1255 qspiSFR->MIXENTRY.U = chHandle->
bacon.U;
1259 qspiSFR->BACONENTRY.U = chHandle->
bacon.U;