iLLD_TC27xD  1.0
IfxMtu_cfg.h
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1 /**
2  * \file IfxMtu_cfg.h
3  * \brief Mtu on-chip implementation data
4  * \ingroup IfxLld_Mtu
5  *
6  * \version iLLD_1_0_0_11_0
7  * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Mtu MTU
25  * \ingroup IfxLld
26  * \defgroup IfxLld_Mtu_Impl Implementation
27  * \ingroup IfxLld_Mtu
28  * \defgroup IfxLld_Mtu_Std Standard Driver
29  * \ingroup IfxLld_Mtu
30  */
31 
32 #ifndef IFXMTU_CFG_H
33 #define IFXMTU_CFG_H 1
34 
35 /******************************************************************************/
36 /*----------------------------------Includes----------------------------------*/
37 /******************************************************************************/
38 
39 #include "Cpu/Std/IfxCpu.h"
40 #include "Cpu/Std/IfxCpu_Intrinsics.h"
41 #include "IfxMtu_reg.h"
42 #include "IfxMc_reg.h"
43 
44 /******************************************************************************/
45 /*-----------------------------------Macros-----------------------------------*/
46 /******************************************************************************/
47 
48 /** \brief Base address of first MBIST Control Block
49  */
50 #define IFXMTU_MC_ADDRESS_BASE (0xF0061000u)
51 
52 /** \brief Number of MBIST Table items
53  */
54 #define IFXMTU_NUM_MBIST_TABLE_ITEMS (84)
55 
56 /** \brief Maximum number of tracked SRAM addresses (ETTR)
57  */
58 #define IFXMTU_MAX_TRACKED_ADDRESSES (5)
59 
60 /******************************************************************************/
61 /*-------------------------------Enumerations---------------------------------*/
62 /******************************************************************************/
63 
64 /** \brief MBIST Selection
65  */
66 typedef enum
67 {
68  IfxMtu_MbistSel_none = -1,
69  IfxMtu_MbistSel_cpu2Dspr = 0,
70  IfxMtu_MbistSel_cpu2Dtag = 2,
71  IfxMtu_MbistSel_cpu2Pspr = 3,
72  IfxMtu_MbistSel_cpu2Ptag = 5,
73  IfxMtu_MbistSel_cpu1Dspr = 6,
74  IfxMtu_MbistSel_cpu1Dtag = 8,
75  IfxMtu_MbistSel_cpu1Pspr = 9,
76  IfxMtu_MbistSel_cpu1Ptag = 11,
77  IfxMtu_MbistSel_cpu0Dspr = 14,
78  IfxMtu_MbistSel_cpu0Pspr = 16,
79  IfxMtu_MbistSel_cpu0Ptag = 17,
80  IfxMtu_MbistSel_ethermac = 22,
81  IfxMtu_MbistSel_mod1 = 23,
82  IfxMtu_MbistSel_mod2 = 24,
83  IfxMtu_MbistSel_mod3 = 25,
84  IfxMtu_MbistSel_mod4 = 26,
85  IfxMtu_MbistSel_gtmFifo = 28,
86  IfxMtu_MbistSel_gtmMcs0 = 29,
87  IfxMtu_MbistSel_gtmMcs1 = 30,
88  IfxMtu_MbistSel_gtmDpll1a = 31,
89  IfxMtu_MbistSel_gtmDpll1b = 32,
90  IfxMtu_MbistSel_gtmDpll2 = 33,
91  IfxMtu_MbistSel_psi5 = 34,
92  IfxMtu_MbistSel_mcan = 36,
93  IfxMtu_MbistSel_erayObf = 38,
94  IfxMtu_MbistSel_erayIbfTbf = 39,
95  IfxMtu_MbistSel_erayMbf = 40,
96  IfxMtu_MbistSel_mcds = 45,
97  IfxMtu_MbistSel_emem0 = 46,
98  IfxMtu_MbistSel_emem1 = 47,
99  IfxMtu_MbistSel_emem2 = 48,
100  IfxMtu_MbistSel_emem3 = 49,
101  IfxMtu_MbistSel_emem4 = 50,
102  IfxMtu_MbistSel_emem5 = 51,
103  IfxMtu_MbistSel_emem6 = 52,
104  IfxMtu_MbistSel_emem7 = 53,
105  IfxMtu_MbistSel_emem8 = 54,
106  IfxMtu_MbistSel_emem9 = 55,
107  IfxMtu_MbistSel_emem10 = 56,
108  IfxMtu_MbistSel_emem11 = 57,
109  IfxMtu_MbistSel_emem12 = 58,
110  IfxMtu_MbistSel_emem13 = 59,
111  IfxMtu_MbistSel_emem14 = 60,
112  IfxMtu_MbistSel_emem15 = 61,
113  IfxMtu_MbistSel_cifJpeg1_4 = 78,
114  IfxMtu_MbistSel_lmu = 79,
115  IfxMtu_MbistSel_cifJpeg3 = 80,
116  IfxMtu_MbistSel_cifCif = 81,
117  IfxMtu_MbistSel_dma = 83
118 } IfxMtu_MbistSel;
119 
120 /******************************************************************************/
121 /*-----------------------------Data Structures--------------------------------*/
122 /******************************************************************************/
123 
124 /** \brief Describes physical parameters of a SRAM memory
125  */
126 typedef struct
127 {
128  uint8 numBlocks; /**< \brief number of SRAM blocks */
129  uint16 dataSize; /**< \brief Data Size of each memory block */
130  uint8 eccSize; /**< \brief ECC Size of each memory block */
131  uint8 eccInvPos0; /**< \brief First ECC bit which needs to be inverted */
132  uint8 eccInvPos1; /**< \brief Second ECC bit which needs to be inverted */
133  uint32 mbistDelay; /**< \brief Mbist Delay */
134 } IfxMtu_SramItem;
135 
136 /******************************************************************************/
137 /*-------------------Global Exported Variables/Constants----------------------*/
138 /******************************************************************************/
139 
140 IFX_EXTERN const IfxMtu_SramItem IfxMtu_sramTable[IFXMTU_NUM_MBIST_TABLE_ITEMS];
141 
142 #endif /* IFXMTU_CFG_H */