iLLD_TC27xD  1.0
IfxMtu_cfg.c
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1 /**
2  * \file IfxMtu_cfg.c
3  * \brief Mtu on-chip implementation data
4  *
5  * \version iLLD_1_0_0_11_0
6  * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  */
24 
25 /******************************************************************************/
26 /*----------------------------------Includes----------------------------------*/
27 /******************************************************************************/
28 
29 #include "IfxMtu_cfg.h"
30 
31 /******************************************************************************/
32 /*-----------------------Exported Variables/Constants-------------------------*/
33 /******************************************************************************/
34 
35 const IfxMtu_SramItem IfxMtu_sramTable[IFXMTU_NUM_MBIST_TABLE_ITEMS] = {
36  {2 * 4, 16, 6, 0, 1, 8192}, /**< \brief IfxMtu_MbistSel_cpu2Dspr */
37  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
38  {2 * 1, 20, 6, 0, 1, 128 }, /**< \brief IfxMtu_MbistSel_cpu2Dtag */
39  {1 * 2, 64, 8, 0, 1, 3072}, /**< \brief IfxMtu_MbistSel_cpu2Pspr */
40  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
41  {2 * 1, 20, 5, 0, 1, 256 }, /**< \brief IfxMtu_MbistSel_cpu2Ptag */
42  {2 * 4, 16, 6, 0, 1, 8192}, /**< \brief IfxMtu_MbistSel_cpu1Dspr */
43  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
44  {2 * 1, 20, 6, 0, 1, 128 }, /**< \brief IfxMtu_MbistSel_cpu1Dtag */
45  {1 * 2, 64, 8, 0, 1, 3072}, /**< \brief IfxMtu_MbistSel_cpu1Pspr */
46  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
47  {2 * 1, 20, 5, 0, 1, 256 }, /**< \brief IfxMtu_MbistSel_cpu1Ptag */
48  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
49  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
50  {2 * 4, 16, 6, 0, 1, 8192}, /**< \brief IfxMtu_MbistSel_cpu0Dspr */
51  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
52  {1 * 2, 32, 8, 0, 1, 3072}, /**< \brief IfxMtu_MbistSel_cpu0Pspr */
53  {2 * 1, 20, 5, 0, 1, 256 }, /**< \brief IfxMtu_MbistSel_cpu0Ptag */
54  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
55  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
56  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
57  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
58  {1 * 2, 35, 7, 0, 1, 1024}, /**< \brief IfxMtu_MbistSel_ethermac */
59  {1 * 4, 32, 8, 0, 1, 256 }, /**< \brief IfxMtu_MbistSel_mod1 */
60  {1 * 4, 24, 6, 0, 1, 64 }, /**< \brief IfxMtu_MbistSel_mod2 */
61  {1 * 2, 32, 8, 0, 1, 5120}, /**< \brief IfxMtu_MbistSel_mod3 */
62  {1 * 1, 64, 8, 0, 1, 4096}, /**< \brief IfxMtu_MbistSel_mod4 */
63  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
64  {1 * 1, 29, 7, 0, 1, 1024}, /**< \brief IfxMtu_MbistSel_gtmFifo */
65  {1 * 4, 32, 8, 0, 1, 1024}, /**< \brief IfxMtu_MbistSel_gtmMcs0 */
66  {1 * 4, 32, 8, 0, 1, 512 }, /**< \brief IfxMtu_MbistSel_gtmMcs1 */
67  {1 * 1, 24, 7, 0, 1, 128 }, /**< \brief IfxMtu_MbistSel_gtmDpll1a */
68  {1 * 1, 24, 7, 0, 1, 384 }, /**< \brief IfxMtu_MbistSel_gtmDpll1b */
69  {1 * 1, 24, 7, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_gtmDpll2 */
70  {1 * 1, 32, 8, 0, 1, 192 }, /**< \brief IfxMtu_MbistSel_psi5 */
71  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
72  {1 * 1, 32, 8, 0, 1, 2368}, /**< \brief IfxMtu_MbistSel_mcan */
73  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
74  {1 * 2, 32, 8, 0, 1, 64 }, /**< \brief IfxMtu_MbistSel_erayObf */
75  {1 * 4, 32, 8, 0, 1, 128 }, /**< \brief IfxMtu_MbistSel_erayIbfTbf */
76  {1 * 1, 32, 8, 0, 1, 4096}, /**< \brief IfxMtu_MbistSel_erayMbf */
77  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
78  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
79  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
80  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
81  {1 * 4, 32, 8, 0, 1, 1024}, /**< \brief IfxMtu_MbistSel_mcds */
82  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem0 */
83  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem1 */
84  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem2 */
85  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem3 */
86  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem4 */
87  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem5 */
88  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem6 */
89  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem7 */
90  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem8 */
91  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem9 */
92  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem10 */
93  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem11 */
94  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem12 */
95  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem13 */
96  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem14 */
97  {1 * 2, 128, 9, 0, 1, 2048}, /**< \brief IfxMtu_MbistSel_emem15 */
98  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
99  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
100  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
101  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
102  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
103  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
104  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
105  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
106  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
107  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
108  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
109  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
110  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
111  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
112  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
113  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
114  {1 * 4, 8, 6, 0, 1, 5120}, /**< \brief IfxMtu_MbistSel_cifJpeg1_4 */
115  {1 * 1, 64, 8, 0, 1, 4096}, /**< \brief IfxMtu_MbistSel_lmu */
116  {1 * 2, 8, 6, 0, 1, 384 }, /**< \brief IfxMtu_MbistSel_cifJpeg3 */
117  {1 * 1, 36, 8, 0, 1, 512 }, /**< \brief IfxMtu_MbistSel_cifCif */
118  {0 * 0, 0, 0, 0, 0, 0 }, /**< \brief IfxMtu_MbistSel_none */
119  {1 * 4, 64, 8, 0, 1, 256 }, /**< \brief IfxMtu_MbistSel_dma */
120 };