49 Ifx_DMA_CH_CHCFGR chcfgr;
57 chcfgr.B.PATSEL = config->
pattern;
59 channel->CHCFGR.U = chcfgr.U;
63 Ifx_DMA_CH_ADICR adicr;
82 channel->ADICR.U = adicr.U;
102 dmaHandle->
dma = dma;
120 IfxDma_Dma_configureTransactionSet(channel->
channel, config);
153 .destinationAddress = 0,
156 .sourceDestinationAddressCrc = 0,
165 .hardwareRequestEnabled =
FALSE,
173 .sourceCircularBufferEnabled =
FALSE,
174 .destinationCircularBufferEnabled =
FALSE,
175 .timestampEnabled =
FALSE,
176 .wrapSourceInterruptEnabled =
FALSE,
177 .wrapDestinationInterruptEnabled =
FALSE,
178 .channelInterruptEnabled =
FALSE,
180 .interruptRaiseThreshold = 0,
181 .transactionRequestLostInterruptEnabled =
FALSE,
182 .channelInterruptPriority = 0,
187 *config = defaultConfig;
196 IfxDma_Dma_configureTransactionSet((Ifx_DMA_CH *)ptrToAddress, config);