iLLD_TC29x  1.0
IfxPsi5s.c
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1 /**
2  * \file IfxPsi5s.c
3  * \brief PSI5S basic functionality
4  *
5  * \version iLLD_1_0_0_11_0
6  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  */
24 
25 /******************************************************************************/
26 /*----------------------------------Includes----------------------------------*/
27 /******************************************************************************/
28 
29 #include "IfxPsi5s.h"
30 
31 /******************************************************************************/
32 /*-------------------------Function Implementations---------------------------*/
33 /******************************************************************************/
34 
35 void IfxPsi5s_enableAscReceiver(Ifx_PSI5S *psi5s)
36 {
37  psi5s->WHBCON.B.SETREN = 1;
38 }
39 
40 
41 void IfxPsi5s_enableDisableChannelTriggerCounters(Ifx_PSI5S *psi5s, uint32 channels, uint32 mask)
42 {
43  uint32 enableChannels = ((((psi5s->GCR.U >> IFX_PSI5S_GCR_ETC0_OFF) & ~mask) | channels) << IFX_PSI5S_GCR_ETC0_OFF);
44 
45  psi5s->GCR.U |= (psi5s->GCR.U & ~IFXPSI5S_GCR_CHANNEL_TRIGGER_COUNTERS_ENABLE_MASK) | enableChannels;
46 }
47 
48 
49 void IfxPsi5s_enableDisableChannels(Ifx_PSI5S *psi5s, uint32 channels, uint32 mask)
50 {
51  uint32 enableChannels = ((((psi5s->GCR.U >> IFX_PSI5S_GCR_CEN0_OFF) & ~mask) | channels) << IFX_PSI5S_GCR_CEN0_OFF);
52 
53  psi5s->GCR.U |= (psi5s->GCR.U & ~IFXPSI5S_GCR_CHANNELS_ENABLE_MASK) | enableChannels;
54 }
55 
56 
57 void IfxPsi5s_resetModule(Ifx_PSI5S *psi5s)
58 {
59  uint16 passwd = IfxScuWdt_getCpuWatchdogPassword();
60 
61  IfxScuWdt_clearCpuEndinit(passwd);
62  psi5s->KRST0.B.RST = 1; /* Only if both Kernel reset bits are set a reset is executed */
63  psi5s->KRST1.B.RST = 1;
64  IfxScuWdt_setCpuEndinit(passwd);
65 
66  while (0 == psi5s->KRST0.B.RSTSTAT) /* Wait until reset is executed */
67 
68  {}
69 
70  IfxScuWdt_clearCpuEndinit(passwd);
71  psi5s->KRSTCLR.B.CLR = 1; /* Clear Kernel reset status bit */
72  IfxScuWdt_setCpuEndinit(passwd);
73 }
74 
75 
76 void IfxPsi5s_startAscTransactions(Ifx_PSI5S *psi5s)
77 {
78  psi5s->CON.B.R = 1;
79 }
80 
81 
82 boolean IfxPsi5s_getReadFrameStatus(Ifx_PSI5S *psi5s, IfxPsi5s_ChannelId channelId)
83 {
84  return psi5s->INTSTAT[channelId].B.RDI;
85 }