iLLD_TC27xD  1.0
IfxScuEru.c
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1 /**
2  * \file IfxScuEru.c
3  * \brief SCU basic functionality
4  *
5  * \version iLLD_1_0_0_11_0
6  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  *
24  */
25 
26 /******************************************************************************/
27 /*----------------------------------Includes----------------------------------*/
28 /******************************************************************************/
29 
30 #include "IfxScuEru.h"
31 
32 /******************************************************************************/
33 /*----------------------------------Macros------------------------------------*/
34 /******************************************************************************/
35 
36 #define IFXSCUERU_CHANNEL_NUMBER_ODD 1
37 
38 #define IFXSCUERU_TO_REGISTER_BASE 1
39 
40 /******************************************************************************/
41 /*-------------------------Function Implementations---------------------------*/
42 /******************************************************************************/
43 
45 {
46  uint32 mask = (0xFF << 16);
47  MODULE_SCU.FMR.U = mask;
48 }
49 
50 
52 {
53  uint32 mask = 1 << (inputChannel + 16);
54  SCU_FMR.U = mask;
55 }
56 
57 
59 {
60  // select appropriate EICRi register for the given input channel X ( i = 0,1,2,3 and X = 0 to 7 )
61  uint32 index = (inputChannel >> IFXSCUERU_TO_REGISTER_BASE);
62  uint32 mask = 0xFFFF;
63 
64  if (inputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
65  {
66  MODULE_SCU.EICR[index].U = (MODULE_SCU.EICR[index].U & mask);
67  }
68  else // for channels 0, 2, 4 and 6
69  {
70  mask = (mask << 16);
71  MODULE_SCU.EICR[index].U = (MODULE_SCU.EICR[index].U & mask);
72  }
73 }
74 
75 
77 {
78  // select appropriate IGCRj register for the given output channel Y ( j = 0,1,2,3 and Y = 0 to 7 )
79  uint32 index = (outputChannel >> IFXSCUERU_TO_REGISTER_BASE);
80  uint32 mask = 0xFFFF;
81 
82  if (outputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
83  {
84  MODULE_SCU.IGCR[index].U = (MODULE_SCU.IGCR[index].U & mask);
85  }
86  else // for channels 0, 2, 4 and 6
87  {
88  mask = (mask << 16);
89  MODULE_SCU.IGCR[index].U = (MODULE_SCU.IGCR[index].U & mask);
90  }
91 }
92 
93 
95 {
96  // select appropriate EICRi register for the given input channel X ( i = 0,1,2,3 and X = 0 to 7 )
97  uint32 index = (inputChannel >> IFXSCUERU_TO_REGISTER_BASE);
98 
99  if (inputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
100  {
101  MODULE_SCU.EICR[index].B.INP1 = triggerSelect;
102  }
103  else // for channels 0, 2, 4 and 6
104  {
105  MODULE_SCU.EICR[index].B.INP0 = triggerSelect;
106  }
107 }
108 
109 
111 {
112  // select appropriate EICRi register for the given input channel X ( i = 0,1,2,3 and X = 0 to 7 )
113  uint32 index = (inputChannel >> IFXSCUERU_TO_REGISTER_BASE);
114 
115  if (inputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
116  {
117  MODULE_SCU.EICR[index].B.LDEN1 = FALSE;
118  }
119  else // for channels 0, 2, 4 and 6
120  {
121  MODULE_SCU.EICR[index].B.LDEN0 = FALSE;
122  }
123 }
124 
125 
127 {
128  // select appropriate EICRi register for the given input channel X ( i = 0,1,2,3 and X = 0 to 7 )
129  uint32 index = (inputChannel >> IFXSCUERU_TO_REGISTER_BASE);
130 
131  if (inputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
132  {
133  MODULE_SCU.EICR[index].B.FEN1 = FALSE;
134  }
135  else // for channels 0, 2, 4 and 6
136  {
137  MODULE_SCU.EICR[index].B.FEN0 = FALSE;
138  }
139 }
140 
141 
143 {
144  // select appropriate IGCRj register for the given output channel Y ( j = 0,1,2,3 and Y = 0 to 7 )
145  uint32 index = (outputChannel >> IFXSCUERU_TO_REGISTER_BASE);
146 
147  if (outputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
148  {
149  MODULE_SCU.IGCR[index].B.GEEN1 = FALSE;
150  }
151  else // for channels 0, 2, 4 and 6
152  {
153  MODULE_SCU.IGCR[index].B.GEEN0 = FALSE;
154  }
155 }
156 
157 
159 {
160  // select appropriate EICRi register for the given input channel X ( i = 0,1,2,3 and X = 0 to 7 )
161  uint32 index = (inputChannel >> IFXSCUERU_TO_REGISTER_BASE);
162 
163  if (inputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
164  {
165  MODULE_SCU.EICR[index].B.REN1 = FALSE;
166  }
167  else // for channels 0, 2, 4 and 6
168  {
169  MODULE_SCU.EICR[index].B.REN0 = FALSE;
170  }
171 }
172 
173 
175 {
176  // select appropriate EICRi register for the given input channel X ( i = 0,1,2,3 and X = 0 to 7 )
177  uint32 index = (inputChannel >> IFXSCUERU_TO_REGISTER_BASE);
178 
179  if (inputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
180  {
181  MODULE_SCU.EICR[index].B.EIEN1 = FALSE;
182  }
183  else // for channels 0, 2, 4 and 6
184  {
185  MODULE_SCU.EICR[index].B.EIEN0 = FALSE;
186  }
187 }
188 
189 
191 {
192  // select appropriate EICRi register for the given input channel X ( i = 0,1,2,3 and X = 0 to 7 )
193  uint32 index = (inputChannel >> IFXSCUERU_TO_REGISTER_BASE);
194 
195  if (inputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
196  {
197  MODULE_SCU.EICR[index].B.LDEN1 = TRUE;
198  }
199  else // for channels 0, 2, 4 and 6
200  {
201  MODULE_SCU.EICR[index].B.LDEN0 = TRUE;
202  }
203 }
204 
205 
207 {
208  // select appropriate EICRi register for the given input channel X ( i = 0,1,2,3 and X = 0 to 7 )
209  uint32 index = (inputChannel >> IFXSCUERU_TO_REGISTER_BASE);
210 
211  if (inputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
212  {
213  MODULE_SCU.EICR[index].B.FEN1 = TRUE;
214  }
215  else // for channels 0, 2, 4 and 6
216  {
217  MODULE_SCU.EICR[index].B.FEN0 = TRUE;
218  }
219 }
220 
221 
223 {
224  // select appropriate IGCRj register for the given output channel Y ( j = 0,1,2,3 and Y = 0 to 7 )
225  uint32 index = (outputChannel >> IFXSCUERU_TO_REGISTER_BASE);
226 
227  if (outputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
228  {
229  MODULE_SCU.IGCR[index].B.GEEN1 = TRUE;
230  }
231  else // for channels 0, 2, 4 and 6
232  {
233  MODULE_SCU.IGCR[index].B.GEEN0 = TRUE;
234  }
235 }
236 
237 
239 {
240  // select appropriate EICRi register for the given input channel X ( i = 0,1,2,3 and X = 0 to 7 )
241  uint32 index = (inputChannel >> IFXSCUERU_TO_REGISTER_BASE);
242 
243  if (inputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
244  {
245  MODULE_SCU.EICR[index].B.REN1 = TRUE;
246  }
247  else // for channels 0, 2, 4 and 6
248  {
249  MODULE_SCU.EICR[index].B.REN0 = TRUE;
250  }
251 }
252 
253 
255 {
256  // select appropriate EICRi register for the given input channel X ( i = 0,1,2,3 and X = 0 to 7 )
257  uint32 index = (inputChannel >> IFXSCUERU_TO_REGISTER_BASE);
258 
259  if (inputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
260  {
261  MODULE_SCU.EICR[index].B.EIEN1 = TRUE;
262  }
263  else // for channels 0, 2, 4 and 6
264  {
265  MODULE_SCU.EICR[index].B.EIEN0 = TRUE;
266  }
267 }
268 
269 
271 {
272  return MODULE_SCU.EIFR.U;
273 }
274 
275 
277 {
278  uint32 mask = (1U << inputChannel);
279  return (MODULE_SCU.EIFR.U & mask) ? TRUE : FALSE;
280 }
281 
282 
284 {
285  // select appropriate EICRi register for the given input channel X ( i = 0,1,2,3 and X = 0 to 7 )
286  uint32 index = (inputChannel >> IFXSCUERU_TO_REGISTER_BASE);
287  uint32 status, mask = 0xFFFF;
288 
289  if (inputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
290  {
291  mask = (mask << 16);
292  status = (MODULE_SCU.EICR[index].U & mask);
293  }
294  else // for channels 0, 2, 4 and 6
295  {
296  status = (MODULE_SCU.EICR[index].U & mask);
297  }
298 
299  return status;
300 }
301 
302 
304 {
305  // select appropriate IGCRj register for the given output channel Y ( j = 0,1,2,3 and Y = 0 to 7 )
306  uint32 index = (outputChannel >> IFXSCUERU_TO_REGISTER_BASE);
307  uint32 status, mask = 0xFFFF;
308 
309  if (outputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
310  {
311  mask = (mask << 16);
312  status = (MODULE_SCU.IGCR[index].U & mask);
313  }
314  else // for channels 0, 2, 4 and 6
315  {
316  status = (MODULE_SCU.IGCR[index].U & mask);
317  }
318 
319  return status;
320 }
321 
322 
324 {
325  uint32 mask = (1U << outputChannel);
326  return (MODULE_SCU.PDRR.U & mask) ? TRUE : FALSE;
327 }
328 
329 
331 {
332  return MODULE_SCU.PDRR.U;
333 }
334 
335 
337 {
338  // select appropriate EICRi register for the given input channel X ( i = 0,1,2,3 and X = 0 to 7 )
339  uint32 index = (inputChannel >> IFXSCUERU_TO_REGISTER_BASE);
340 
341  if (inputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
342  {
343  MODULE_SCU.EICR[index].B.EXIS1 = inputSignal;
344  }
345  else // for channels 0, 2, 4 and 6
346  {
347  MODULE_SCU.EICR[index].B.EXIS0 = inputSignal;
348  }
349 }
350 
351 
353 {
354  uint32 mask = 1 << inputChannel;
355  SCU_FMR.U = mask;
356 }
357 
358 
360 {
361  uint32 shift, mask;
362 
363  if (outputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
364  {
365  shift = (inputChannel + 16); // offset at location IPEN10
366  mask = (1 << shift);
367  // select appropriate IGCRj register for the given output channel Y ( j = 0,1,2,3 and Y = 0 to 7 )
368  uint32 index = (outputChannel >> IFXSCUERU_TO_REGISTER_BASE);
369  MODULE_SCU.IGCR[index].U = (MODULE_SCU.IGCR[index].U & ~mask) | ((uint32)state << shift);
370  }
371  else // for channels 0, 2, 4 and 6
372  {
373  shift = inputChannel;
374  mask = (1 << shift);
375  // select appropriate IGCRj register for the given output channel Y ( j = 0,1,2,3 and Y = 0 to 7 )
376  uint32 index = (outputChannel >> IFXSCUERU_TO_REGISTER_BASE);
377  MODULE_SCU.IGCR[index].U = (MODULE_SCU.IGCR[index].U & ~mask) | ((uint32)state << shift);
378  }
379 }
380 
381 
383 {
384  // select appropriate IGCRj register for the given output channel Y ( j = 0,1,2,3 and Y = 0 to 7 )
385  uint32 index = (outputChannel >> IFXSCUERU_TO_REGISTER_BASE);
386 
387  if (outputChannel & IFXSCUERU_CHANNEL_NUMBER_ODD) // for channels 1, 3 ,5 and 7
388  {
389  MODULE_SCU.IGCR[index].B.IGP1 = gatingPattern;
390  }
391  else // for channels 0, 2, 4 and 6
392  {
393  MODULE_SCU.IGCR[index].B.IGP0 = gatingPattern;
394  }
395 }