iLLD_TC27xD  1.0
IfxHssl_Hssl.c
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1 /**
2  * \file IfxHssl_Hssl.c
3  * \brief HSSL HSSL details
4  *
5  * \version iLLD_1_0_0_11_0
6  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  *
24  */
25 
26 /******************************************************************************/
27 /*----------------------------------Includes----------------------------------*/
28 /******************************************************************************/
29 
30 #include "IfxHssl_Hssl.h"
31 
32 /******************************************************************************/
33 /*-------------------------Function Implementations---------------------------*/
34 /******************************************************************************/
35 
37 {
38  Ifx_HSSL *hsslSFR = hssl->hssl; // pointer to HSSL registers
39 
40  // store the errors in the structure //
41  if (hsslSFR->MFLAGS.B.NACK != 0)
42  {
44  }
45 
46  if (hsslSFR->MFLAGS.B.TTE != 0)
47  {
49  }
50 
51  if (hsslSFR->MFLAGS.B.TIMEOUT != 0)
52  {
53  hssl->errorFlags.timeoutError = 1;
54  }
55 
56  if (hsslSFR->MFLAGS.B.UNEXPECTED != 0)
57  {
58  hssl->errorFlags.unexpectedError = 1;
59  }
60 
61  if (hsslSFR->MFLAGS.B.MAV != 0)
62  {
64  }
65 
66  if (hsslSFR->MFLAGS.B.SRIE != 0)
67  {
68  hssl->errorFlags.busAccessError = 1;
69  }
70 
71  if (hsslSFR->MFLAGS.B.PIE1 != 0)
72  {
74  }
75 
76  if (hsslSFR->MFLAGS.B.PIE2 != 0)
77  {
78  hssl->errorFlags.dataLengthError = 1;
79  }
80 
81  if (hsslSFR->MFLAGS.B.CRCE != 0)
82  {
83  hssl->errorFlags.crcError = 1;
84  }
85 }
86 
87 
89 {
92  hssl->errorFlags.timeoutError = 0;
93  hssl->errorFlags.unexpectedError = 0;
95  hssl->errorFlags.busAccessError = 0;
97  hssl->errorFlags.dataLengthError = 0;
98  hssl->errorFlags.crcError = 0;
99 }
100 
101 
103 {
104  uint32 i;
105 
106  for (i = 0; i < 8000; i++)
107  {
108  __nop();
109  }
110 }
111 
112 
114 {
115  channel->hssl = channelConfig->hssl; // adding HSSL register pointer to channel handle
116  channel->hsct = channelConfig->hsct; // adding HSCT register pointer to channel handle
117 
118  channel->channelId = channelConfig->channelId; // adding channel id to channel handle
119  channel->currentFrameRequest = IfxHssl_Hssl_FrameRequest_noAction; // default request, no action
120 
121  channel->streamingModeOn = FALSE; // command mode (used in waitAcknowledge function)
122  channel->streamingMode = channelConfig->streamingMode; // adding streaming mode to channel handle
123  channel->loopBack = channelConfig->loopBack; // adding loopback selection to channel handle
124 }
125 
126 
128 {
129  channelConfig->hssl = hssl->hssl;
130  channelConfig->hsct = hsct->hsct;
131 
132  channelConfig->channelId = IfxHssl_ChannelId_0; /* default channel 0 */
133  channelConfig->streamingMode = IfxHssl_StreamingMode_single; /* default streaming mode continuous */
134  channelConfig->loopBack = hssl->loopBack;
135 }
136 
137 
139 {
140  Ifx_HSCT *hsctSFR = config->hsct; // pointer to HSCT registers
141 
142  hsct->hsct = hsctSFR; // adding HSCT register pointer to module handle
143 
144  // Pad initialisiation //
149 
150  // select the clock direction //
152  {
155  }
156  else
157  {
158  IfxPort_setPinModeInput(&MODULE_P20, 0, IfxPort_InputMode_pullDown); // CLKIN
159  }
160 
161  // LVDS configuration //
162  {
164  IfxScuWdt_clearCpuEndinit(psw); // clears the endinit protection
165 
166 #if 0
167  P21_LPCR1.B.RDIS_CTRL = 1;
168  P21_LPCR1.B.RX_DIS = 0;
169 #else
170  // FIXME: change to original code once new IfxPort_reg.h is available //
171  P21_LPCR1.B_P21.RDIS_CTRL = 1;
172  P21_LPCR1.B_P21.RX_DIS = 0;
173 #endif
174  P21_LPCR2.B.TDIS_CTRL = 1;
175  P21_LPCR2.B.TX_DIS = 0;
176  P21_LPCR2.B.TX_PD = 0;
177 
178  IfxScuWdt_setCpuEndinit(psw); // sets the endinit protection back on
179  }
180 
181  // HSCT initialisation //
182  IfxHssl_enableHsctModule(hsctSFR); // enabling the HSCT module
183 
184  hsctSFR->IRQCLR.B.TXTECLR = 1; // due to AI
185 
186  // slave interface initialisation //
187  if (config->interfaceMode == IfxHssl_InterfaceMode_slave) // slave mode initialisation
188  {
189  hsctSFR->INIT.B.IFM = IfxHssl_InterfaceMode_slave; // slave mode
190  hsctSFR->INIT.B.SYS_CLK_EN = 0; // disabling the system clock
191  hsctSFR->INIT.B.SRCF = IfxHssl_ClockFrequencyRate_20Mhz; // Reference Clock Frequency rate 20 MHz
192  hsctSFR->CONFIGPHY.B.OSCCLKEN = IfxHssl_PllReferenceClock_hsctSystemClockInput; // PLL reference clock is hsct system clock input
193  hsctSFR->CONFIGPHY.B.PHYRST = 0; // disable PHY reset
194  hsctSFR->CONFIGPHY.B.PLLWMF = 16; // PLL frequency control word multiplication factor
195  // enable slave Tx channel (Rx disable to Rx low peed) //
197 
198  // change from low speed to high speed //
199  if (config->highSpeedMode)
200  {
201  hsctSFR->CONFIGPHY.B.OSCCLKEN = IfxHssl_PllReferenceClock_oscillatorInput; // PLL reference clock is Oscillator input
202  // Slave interface clock multiplier off to Slave interface high speed clock
204 
205  // change the speed of slave Rx channel (Tx low speed to Tx high speed)
207 
208  // change the speed of slave Tx channel (Rx disable to Rx low speed)
210  }
211  }
212 
213  // master interface initialisation //
214  else // master mode initialisation
215  {
216  hsctSFR->INIT.B.IFM = IfxHssl_InterfaceMode_master; // master mode
217  hsctSFR->INIT.B.SYS_CLK_EN = 1; // enabling the system clock
218  hsctSFR->INIT.B.SRCF = IfxHssl_ClockFrequencyRate_20Mhz; // Reference Clock Frequency rate 20 MHz
219  hsctSFR->CONFIGPHY.B.OSCCLKEN = IfxHssl_PllReferenceClock_oscillatorInput; // PLL reference clock is Oscillator input
220  hsctSFR->CONFIGPHY.B.PHYRST = 0; // disable PHY reset
221  hsctSFR->CONFIGPHY.B.PLLPON = 1; // PLL power on
222  hsctSFR->CONFIGPHY.B.PLLWMF = 16; // PLL frequency control word multiplication factor
223  hsctSFR->IFCTRL.B.MTXSPEED = IfxHssl_MasterModeTxSpeed_lowSpeed; // Tx low speed
224  hsctSFR->IFCTRL.B.MRXSPEED = IfxHssl_MasterModeRxSpeed_lowSpeed; // Rx low speed
225 
226  // change from low speed to high speed //
227  if (config->highSpeedMode)
228  {
229  hsctSFR->IFCTRL.B.MTXSPEED = IfxHssl_MasterModeTxSpeed_highSpeed; // Tx high speed
230  hsctSFR->IFCTRL.B.MRXSPEED = IfxHssl_MasterModeRxSpeed_highSpeed; // Rx high speed
231  }
232 
233  while (hsctSFR->STATPHY.B.PLOCK == 0) // wait until pll is locked
234  {}
235  }
236 
237  hsctSFR->DISABLE.U = 0;
238 }
239 
240 
242 {
243  config->hsct = hsct;
244 
245  /* interface mode */
247 
248  /* high speed mode disabled */
249  config->highSpeedMode = FALSE;
250 }
251 
252 
254 {
255  Ifx_HSSL *hsslSFR = config->hssl; /* pointer to HSSL registers */
256 
257  hssl->hssl = hsslSFR; /* adding HSSL register pointer to module handle */
258 
259  /* HSSL initialisation */
260  IfxHssl_enableHsslModule(hsslSFR); /* enabling the HSSL module */
261  hsslSFR->CFG.B.PREDIV = config->preDivider; /* predivivder */
262  hsslSFR->CFG.B.SCM = 0; /* command mode */
263 
264  /* Access windows */
265  hsslSFR->AW[0].AWSTART.U = config->accessWindow0.start; /* start of access window */
266  hsslSFR->AW[0].AWEND.U = config->accessWindow0.end; /* end of access window */
267  hsslSFR->AW[1].AWSTART.U = config->accessWindow1.start; /* start of access window */
268  hsslSFR->AW[1].AWEND.U = config->accessWindow1.end; /* end of access window */
269  hsslSFR->AW[2].AWSTART.U = config->accessWindow2.start; /* start of access window */
270  hsslSFR->AW[2].AWEND.U = config->accessWindow2.end; /* end of access window */
271  hsslSFR->AW[3].AWSTART.U = config->accessWindow3.start; /* start of access window */
272  hsslSFR->AW[3].AWEND.U = config->accessWindow3.end; /* end of access window */
273 
274  hsslSFR->AR.U = 0x000000ff; /* allow read/write access for all windows */
275 
276  hsslSFR->MFLAGSCL.B.INIC = 1; /* chnage into run mode */
277 
278  while (hsslSFR->MFLAGS.B.INI) /* wait until the mode changes */
279  {}
280 
281  hssl->loopBack = config->loopBack; /* adding loopback selection to module handle */
282 }
283 
284 
286 {
287  config->hssl = hssl;
288 
289  /* Access windows */
290  config->accessWindow0.start = 0x00000000; /* start of access window */
291  config->accessWindow0.end = 0xffffffff; /* end of access window */
292  config->accessWindow1.start = 0x00000000; /* start of access window */
293  config->accessWindow1.end = 0xffffffff; /* end of access window */
294  config->accessWindow2.start = 0x00000000; /* start of access window */
295  config->accessWindow2.end = 0xffffffff; /* end of access window */
296  config->accessWindow3.start = 0x00000000; /* start of access window */
297  config->accessWindow3.end = 0xffffffff; /* end of access window */
298 
299  /* predivider */
300  config->preDivider = 256;
301 
302  config->loopBack = FALSE; /* default with out loopback */
303 }
304 
305 
307 {
308  IfxHssl_ChannelId channelId = channel->channelId;
309 
310  // target start address to memeroy block 0 on target device (writing into HSSL_TSSA0 of the target) //
312 
314  {}
315 
316  // memory count into target reload count register on target device //
318 
320  {}
321 
322  // incase of transfers between two different devices (loopback off) //
323  if (!channel->loopBack)
324  {
325  channel->channelId = IfxHssl_ChannelId_2; // channel 2 for for setting the target device into streaming mode
326 
327  // enable streaming mode (single) of channel 2 on target device //
329 
331  {}
332 
333  // since channel 2 is set to streaming mode register access is no longer possible through it //
334  channel->channelId = channelId; // back to original channel for register access to set MFLGSSET.TSES bit of target device
335 
336  // enable streaming on target device //
338 
340  {}
341  }
342 
343  channel->streamingModeOn = TRUE; // for waitAcknowledge function
344  // preperation was successful //
345  return IfxHssl_Hssl_Status_ok;
346 }
347 
348 
350 {
351  uint32 data = 0; // not required, data will be read back
352  return IfxHssl_Hssl_singleFrameRequest(channel, IfxHssl_Hssl_FrameRequest_readFrame, address, data, dataLength); // initiate the read request
353 }
354 
355 
357 {
358  Ifx_HSCT *hsctSFR = hsct->hsct;
359 
360  hsctSFR->IFCTRL.B.IFCVS = command; /* write the command into the register */
361  hsctSFR->IFCTRL.B.SIFCV = 1; /* activate the command */
362 
363  IfxHssl_Hssl_delay(hsct); /* wait until the change happens */
364 }
365 
366 
368 {
369  Ifx_HSSL_I *hsslI = (Ifx_HSSL_I *)&channel->hssl->I[channel->channelId];
370 
372  {
374  }
375 
376  hsslI->ICON.B.DATLEN = dataLength; // 0x2 -> word size
377  hsslI->ICON.B.TOREL = 0xff; // max reload value
378 
379  switch (frameRequest)
380  {
382  hsslI->ICON.B.RWT = IfxHssl_Command_readFrame;
383  hsslI->IRWA.U = address;
384  break;
386  hsslI->ICON.B.RWT = IfxHssl_Command_writeFrame;
387  hsslI->IWD.U = data;
388  hsslI->IRWA.U = address;
389  break;
391  hsslI->ICON.B.RWT = IfxHssl_Command_triggerFrame;
392  hsslI->IWD.U = data; // dummy
393  hsslI->IRWA.U = address; // dummy
394  break;
396  // request an ID frame //
397  channel->hssl->TIDADD.U = address;
398  hsslI->ICON.B.IDQ = 1;
399  break;
400  default:
401  // invalid request //
403  }
404 
405  channel->currentFrameRequest = frameRequest;
406 
407  return IfxHssl_Hssl_Status_ok;
408 }
409 
410 
412 {
413  uint32 requestType = channel->currentFrameRequest;
414  IfxHssl_ChannelId channelId = channel->channelId;
415 
416  if ((channelId == IfxHssl_ChannelId_2) && (channel->streamingModeOn))
417  {
418  while (channel->hssl->MFLAGS.B.ISB)
419  {
420  // transfer in progress
421  }
422  }
423  else
424  {
426  {
427  requestType = 1;
428  }
429 
430  // expect a read frame when requestType == IfxHssl_Hssl_FrameRequest_readId //
432  {
433  requestType = 2;
434  }
435 
437  {
438  requestType = 3;
439  }
440 
441  uint32 qFlags = channel->hssl->QFLAGS.U;
442  uint32 mFlags = channel->hssl->MFLAGS.U;
443  uint32 acknwoledgeFlagsMask = ((requestType << (16 + (channel->channelId * 2))) | (1 << channel->channelId));
444  uint32 errorFlagsMask = ((0x03E00000) | (4369 << channel->channelId)); // all the possible errors
445 
446  if (qFlags & acknwoledgeFlagsMask) // transfer in progress?
447  {
448  if (mFlags & errorFlagsMask) // check for errors
449  {
451  return IfxHssl_Hssl_Status_error; // return error status in case of an error
452  }
453  else
454  {
455  return IfxHssl_Hssl_Status_busy; // return busy status in case of no error
456  }
457  }
458 
459  // transfer is finished //
461  }
462 
463  return IfxHssl_Hssl_Status_ok;
464 }
465 
466 
468 {
469  return IfxHssl_Hssl_singleFrameRequest(channel, IfxHssl_Hssl_FrameRequest_writeFrame, address, data, dataLength);
470 }
471 
472 
474 {
475  Ifx_HSSL *hsslSFR = hssl->hssl;
476  Ifx_HSSL_IS *hsslIS = (Ifx_HSSL_IS *)&hsslSFR->IS;
478 
479  // single memory block streaming //
480  hsslIS->SA[0].U = (uint32)data; // initiator start address to memeroy block 0
481 
482  hsslIS->FC.B.RELCOUNT = count; // memory count into initiator reload count register
483 
484  hsslSFR->CFG.B.SCM = 1; // enable streaming mode of channel 2 on the initiator
485  hsslSFR->CFG.B.SMT = streamingMode; // set transmitter streaming mode ( single / continuous ) on the initiator
486  hsslSFR->CFG.B.SMR = streamingMode; // set receiver streaming mode ( single / continuous ) on the initiator
487 
488  // incase of transfers within the device(loopback on) //
489  if (hssl->loopBack)
490  {
491  hsslSFR->MFLAGSSET.B.TSES = 1; // enable target
492  }
493 
494  // initiate the transfer //
495  hsslSFR->MFLAGSSET.B.ISBS = 1;
496 
497  // streaming started //
498  return IfxHssl_Hssl_Status_ok;
499 }