iLLD_TC27xD  1.0
IfxGtm_cfg.h
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1 /**
2  * \file IfxGtm_cfg.h
3  * \brief GTM on-chip implementation data
4  * \ingroup IfxLld_Gtm
5  *
6  * \version iLLD_1_0_0_11_0
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Gtm GTM
25  * \ingroup IfxLld
26  * \defgroup IfxLld_Gtm_Impl Implementation
27  * \ingroup IfxLld_Gtm
28  * \defgroup IfxLld_Gtm_Std Standard Driver
29  * \ingroup IfxLld_Gtm
30  * \defgroup IfxLld_Gtm_Atom Atom Interface Drivers
31  * \ingroup IfxLld_Gtm
32  * \defgroup IfxLld_Gtm_Tom TOM Interface Drivers
33  * \ingroup IfxLld_Gtm
34  * \defgroup IfxLld_Gtm_Impl_Enumerations Enumerations
35  * \ingroup IfxLld_Gtm_Impl
36  * \defgroup IfxLld_Gtm_Impl_Data_Structures Data Structures
37  * \ingroup IfxLld_Gtm_Impl
38  */
39 
40 #ifndef IFXGTM_CFG_H
41 #define IFXGTM_CFG_H 1
42 
43 /******************************************************************************/
44 /*----------------------------------Includes----------------------------------*/
45 /******************************************************************************/
46 
47 #include "Cpu/Std/IfxCpu_Intrinsics.h"
48 #include "Ifx_Cfg.h"
49 #include "IfxGtm_reg.h"
50 #include "Port/Std/IfxPort.h"
51 
52 /******************************************************************************/
53 /*-----------------------------------Macros-----------------------------------*/
54 /******************************************************************************/
55 
56 /** \brief Mask for CMU_CLK_EN register (Enable): CLK0
57  */
58 #define IFXGTM_CMU_CLKEN_CLK0 (0x00000002)
59 
60 /** \brief Mask for CMU_CLK_EN register (Enable): CLK1
61  */
62 #define IFXGTM_CMU_CLKEN_CLK1 (0x00000008)
63 
64 /** \brief Mask for CMU_CLK_EN register (Enable): CLK2
65  */
66 #define IFXGTM_CMU_CLKEN_CLK2 (0x00000020)
67 
68 /** \brief Mask for CMU_CLK_EN register (Enable): CLK3
69  */
70 #define IFXGTM_CMU_CLKEN_CLK3 (0x00000080)
71 
72 /** \brief Mask for CMU_CLK_EN register (Enable): CLK4
73  */
74 #define IFXGTM_CMU_CLKEN_CLK4 (0x00000200)
75 
76 /** \brief Mask for CMU_CLK_EN register (Enable): CLK5
77  */
78 #define IFXGTM_CMU_CLKEN_CLK5 (0x00000800)
79 
80 /** \brief Mask for CMU_CLK_EN register (Enable): CLK6
81  */
82 #define IFXGTM_CMU_CLKEN_CLK6 (0x00002000)
83 
84 /** \brief Mask for CMU_CLK_EN register (Enable): CLK7
85  */
86 #define IFXGTM_CMU_CLKEN_CLK7 (0x00008000)
87 
88 /** \brief Mask for CMU_CLK_EN register (Enable): ECLK0
89  */
90 #define IFXGTM_CMU_CLKEN_ECLK0 (0x00020000)
91 
92 /** \brief Mask for CMU_CLK_EN register (Enable): ECLK1
93  */
94 #define IFXGTM_CMU_CLKEN_ECLK1 (0x00080000)
95 
96 /** \brief Mask for CMU_CLK_EN register (Enable): ECLK2
97  */
98 #define IFXGTM_CMU_CLKEN_ECLK2 (0x00200000)
99 
100 /** \brief Mask for CMU_CLK_EN register (Enable): FXCLK
101  */
102 #define IFXGTM_CMU_CLKEN_FXCLK (0x00800000)
103 
104 /** \brief Mask for CMU_CLK_EN register (Enable): ALL clocks
105  */
106 #define IFXGTM_CMU_CLKEN_ALL (0x00AAAAAA)
107 
108 /** \brief Mask for CMU_CLK_EN register (Disable): CLK0
109  */
110 #define IFXGTM_CMU_CLKDIS_CLK0 (0x00000001)
111 
112 /** \brief Mask for CMU_CLK_EN register (Disable): CLK1
113  */
114 #define IFXGTM_CMU_CLKDIS_CLK1 (0x00000004)
115 
116 /** \brief Mask for CMU_CLK_EN register (Disable): CLK2
117  */
118 #define IFXGTM_CMU_CLKDIS_CLK2 (0x00000010)
119 
120 /** \brief Mask for CMU_CLK_EN register (Disable): CLK3
121  */
122 #define IFXGTM_CMU_CLKDIS_CLK3 (0x00000040)
123 
124 /** \brief Mask for CMU_CLK_EN register (Disable): CLK4
125  */
126 #define IFXGTM_CMU_CLKDIS_CLK4 (0x00000100)
127 
128 /** \brief Mask for CMU_CLK_EN register (Disable): CLK5
129  */
130 #define IFXGTM_CMU_CLKDIS_CLK5 (0x00000400)
131 
132 /** \brief Mask for CMU_CLK_EN register (Disable): CLK6
133  */
134 #define IFXGTM_CMU_CLKDIS_CLK6 (0x00001000)
135 
136 /** \brief Mask for CMU_CLK_EN register (Disable): CLK7
137  */
138 #define IFXGTM_CMU_CLKDIS_CLK7 (0x00004000)
139 
140 /** \brief Mask for CMU_CLK_EN register (Disable): ECLK0
141  */
142 #define IFXGTM_CMU_CLKDIS_ECLK0 (0x00010000)
143 
144 /** \brief Mask for CMU_CLK_EN register (Disable): ECLK1
145  */
146 #define IFXGTM_CMU_CLKDIS_ECLK1 (0x00040000)
147 
148 /** \brief Mask for CMU_CLK_EN register (Disable): ECLK2
149  */
150 #define IFXGTM_CMU_CLKDIS_ECLK2 (0x00100000)
151 
152 /** \brief Mask for CMU_CLK_EN register (Disable): FXCLK
153  */
154 #define IFXGTM_CMU_CLKDIS_FXCLK (0x00400000)
155 
156 /** \brief Mask for CMU_CLK_EN register (Disable): ALL clocks
157  */
158 #define IFXGTM_CMU_CLKDIS_ALL (0x00555555)
159 
160 #define IFXGTM_NUM_ATOM_OBJECTS (5)
161 
162 #define IFXGTM_NUM_TOM_OBJECTS (3)
163 
164 /******************************************************************************/
165 /*------------------------------Type Definitions------------------------------*/
166 /******************************************************************************/
167 
168 typedef volatile struct IfxGtm_Tom_TGC Ifx_GTM_TOM_TGC;
169 
170 /******************************************************************************/
171 /*--------------------------------Enumerations--------------------------------*/
172 /******************************************************************************/
173 
174 /** \addtogroup IfxLld_Gtm_Impl_Enumerations
175  * \{ */
176 /** \brief Enum for ATOM objects
177  */
178 typedef enum
179 {
180  IfxGtm_Atom_0, /**< \brief ATOM object 0 */
181  IfxGtm_Atom_1, /**< \brief ATOM object 1 */
182  IfxGtm_Atom_2, /**< \brief ATOM object 2 */
183  IfxGtm_Atom_3, /**< \brief ATOM object 3 */
184  IfxGtm_Atom_4 /**< \brief ATOM object 4 */
185 } IfxGtm_Atom;
186 
187 /** \brief Enum for ATOM channels
188  */
189 typedef enum
190 {
191  IfxGtm_Atom_Ch_none = -1, /**< \brief Not Selected */
192  IfxGtm_Atom_Ch_0, /**< \brief ATOM channel 0 */
193  IfxGtm_Atom_Ch_1, /**< \brief ATOM channel 1 */
194  IfxGtm_Atom_Ch_2, /**< \brief ATOM channel 2 */
195  IfxGtm_Atom_Ch_3, /**< \brief ATOM channel 3 */
196  IfxGtm_Atom_Ch_4, /**< \brief ATOM channel 4 */
197  IfxGtm_Atom_Ch_5, /**< \brief ATOM channel 5 */
198  IfxGtm_Atom_Ch_6, /**< \brief ATOM channel 6 */
199  IfxGtm_Atom_Ch_7 /**< \brief ATOM channel 7 */
200 } IfxGtm_Atom_Ch;
201 
202 /** \brief Enum for Dpll subincrements
203  */
204 typedef enum
205 {
206  IfxGtm_Dpll_SubInc_1 = 0, /**< \brief subincrement1 */
207  IfxGtm_Dpll_SubInc_2 /**< \brief subincrement2 */
208 } IfxGtm_Dpll_SubInc;
209 
210 /** \brief Enum Enable disable feature control
211  */
212 typedef enum
213 {
214  IfxGtm_FeatureControl_disabled = 0, /**< \brief disabled */
215  IfxGtm_FeatureControl_disable = 1, /**< \brief disable */
216  IfxGtm_FeatureControl_enable = 2, /**< \brief enable */
217  IfxGtm_FeatureControl_enabled = 3 /**< \brief enabled */
218 } IfxGtm_FeatureControl;
219 
220 /** \brief Enum for TIM objects
221  */
222 typedef enum
223 {
224  IfxGtm_Tim_0, /**< \brief TIM object 0 */
225  IfxGtm_Tim_1, /**< \brief TIM object 1 */
226  IfxGtm_Tim_2, /**< \brief TIM object 2 */
227  IfxGtm_Tim_3 /**< \brief TIM object 3 */
228 } IfxGtm_Tim;
229 
230 /** \brief Enum for TIM channels
231  */
232 typedef enum
233 {
234  IfxGtm_Tim_Ch_0, /**< \brief TIM channel 0 */
235  IfxGtm_Tim_Ch_1, /**< \brief TIM channel 1 */
236  IfxGtm_Tim_Ch_2, /**< \brief TIM channel 2 */
237  IfxGtm_Tim_Ch_3, /**< \brief TIM channel 3 */
238  IfxGtm_Tim_Ch_4, /**< \brief TIM channel 4 */
239  IfxGtm_Tim_Ch_5, /**< \brief TIM channel 5 */
240  IfxGtm_Tim_Ch_6, /**< \brief TIM channel 6 */
241  IfxGtm_Tim_Ch_7 /**< \brief TIM channel 7 */
242 } IfxGtm_Tim_Ch;
243 
244 /** \brief Enum for TOM objects
245  */
246 typedef enum
247 {
248  IfxGtm_Tom_0, /**< \brief TOM object 0 */
249  IfxGtm_Tom_1, /**< \brief TOM object 1 */
250  IfxGtm_Tom_2 /**< \brief TOM object 2 */
251 } IfxGtm_Tom;
252 
253 /** \brief Enum for TOM channels
254  */
255 typedef enum
256 {
257  IfxGtm_Tom_Ch_none = -1, /**< \brief Not Selected */
258  IfxGtm_Tom_Ch_0, /**< \brief TOM channel 0 */
259  IfxGtm_Tom_Ch_1, /**< \brief TOM channel 1 */
260  IfxGtm_Tom_Ch_2, /**< \brief TOM channel 2 */
261  IfxGtm_Tom_Ch_3, /**< \brief TOM channel 3 */
262  IfxGtm_Tom_Ch_4, /**< \brief TOM channel 4 */
263  IfxGtm_Tom_Ch_5, /**< \brief TOM channel 5 */
264  IfxGtm_Tom_Ch_6, /**< \brief TOM channel 6 */
265  IfxGtm_Tom_Ch_7, /**< \brief TOM channel 7 */
266  IfxGtm_Tom_Ch_8, /**< \brief TOM channel 8 */
267  IfxGtm_Tom_Ch_9, /**< \brief TOM channel 9 */
268  IfxGtm_Tom_Ch_10, /**< \brief TOM channel 10 */
269  IfxGtm_Tom_Ch_11, /**< \brief TOM channel 11 */
270  IfxGtm_Tom_Ch_12, /**< \brief TOM channel 12 */
271  IfxGtm_Tom_Ch_13, /**< \brief TOM channel 13 */
272  IfxGtm_Tom_Ch_14, /**< \brief TOM channel 14 */
273  IfxGtm_Tom_Ch_15 /**< \brief TOM channel 15 */
274 } IfxGtm_Tom_Ch;
275 
276 /** \brief Enum for TOM global channel control units
277  */
278 typedef enum
279 {
280  IfxGtm_Tom_Tgc_0, /**< \brief TOM global channel control unit0 */
281  IfxGtm_Tom_Tgc_1 /**< \brief TOM global channel control unit1 */
282 } IfxGtm_Tom_Tgc;
283 
284 /** \} */
285 
286 /******************************************************************************/
287 /*-----------------------------Data Structures--------------------------------*/
288 /******************************************************************************/
289 
290 /** \addtogroup IfxLld_Gtm_Impl_Data_Structures
291  * \{ */
292 /** \brief TOM TGC objects
293  */
294 struct IfxGtm_Tom_TGC
295 {
296  Ifx_GTM_TOM_TGC0_GLB_CTRL GLB_CTRL; /**< \brief 30, TOM TGC0 Global Control Register */
297  Ifx_GTM_TOM_TGC0_ACT_TB ACT_TB; /**< \brief 34, TOM TGC0 Action Time Base Register */
298  Ifx_GTM_TOM_TGC0_FUPD_CTRL FUPD_CTRL; /**< \brief 38, TOM TGC0 Force Update Control Register */
299  Ifx_GTM_TOM_TGC0_INT_TRIG INT_TRIG; /**< \brief 3C, TOM TGC0 Internal Trigger Control Register */
300  Ifx_GTM_TOM_CH xxxCH1; /**< \brief 40, TOM channel objects */
301  Ifx_GTM_TOM_TGC0_ENDIS_CTRL ENDIS_CTRL; /**< \brief 70, TOM TGC0 Enable/Disable Control Register */
302  Ifx_GTM_TOM_TGC0_ENDIS_STAT ENDIS_STAT; /**< \brief 74, TOM TGC0 Enable/Disable Status Register */
303  Ifx_GTM_TOM_TGC0_OUTEN_CTRL OUTEN_CTRL; /**< \brief 78, TOM TGC0 Output Enable Control Register */
304  Ifx_GTM_TOM_TGC0_OUTEN_STAT OUTEN_STAT; /**< \brief 7C, TOM TGC0 Output Enable Status Register */
305 };
306 
307 /** \} */
308 
309 #endif /* IFXGTM_CFG_H */