30 #include "IfxGtm_bf.h"
39 #define IFXGTM_TOM_NUM_TGC_CHANNELS (8)
48 tomCh->IRQ_NOTIFY.B.CCU1TC = 1;
56 tomCh->IRQ_NOTIFY.B.CCU0TC = 1;
90 clock = tomCh->CTRL.B.CLK_SRC_SR;
108 return (
volatile uint32 *)&tomCh->CM1.U;
123 return (
volatile uint32 *)&tomCh->CM0.U;
132 result = tomCh->STAT.B.OL == 1;
140 return &MODULE_SRC.GTM.GTM[0].TOM[tom][channel / 2];
164 return (
volatile uint32 *)&tomCh->CN0.U;
173 result = tomCh->IRQ_NOTIFY.B.CCU1TC != 0;
184 result = tomCh->IRQ_NOTIFY.B.CCU0TC != 0;
194 tomCh->IRQ_FORCINT.B.TRG_CCU1TC0 = 1;
202 tomCh->IRQ_FORCINT.B.TRG_CCU0TC0 = 1;
210 tomCh->CTRL.B.CLK_SRC_SR = clock;
218 tomCh->CM0.U = compareZero;
219 tomCh->CM1.U = compareOne;
227 tomCh->CM1.U = compareOne;
235 tomCh->SR1.U = shadowOne;
243 tomCh->SR0.U = shadowZero;
244 tomCh->SR1.U = shadowOne;
252 tomCh->CM0.U = compareZero;
260 tomCh->SR0.U = shadowZero;
268 tomCh->CN0.U = value;
278 tomCh->CTRL.B.GCM = enabled ? 1 : 0;
287 Ifx_GTM_TOM_CH_IRQ_EN en;
288 en.U = tomCh->IRQ_EN.U;
292 tomCh->IRQ_MODE.B.IRQ_MODE = mode;
293 tomCh->IRQ_EN.U = en.U;
295 en.B.CCU0TC_IRQ_EN = interruptOnCompareZero ? 1 : 0;
296 en.B.CCU1TC_IRQ_EN = interruptOnCompareOne ? 1 : 0;
297 tomCh->IRQ_EN.U = en.U;
305 tomCh->CTRL.B.OSM = enabled ? 1 : 0;
313 tom->CH15.CTRL.B.BITREV = enabled ? 1 : 0;
322 tomCh->CTRL.B.RST_CCU0 = event;
340 tomCh->CTRL.B.SPEM = enabled ? 1 : 0;
349 tomCh->CTRL.B.TRIGOUT = trigger;
357 uint32 mask = enableMask | (disableMask << 16);
362 uint8 shift = (i * 2) + bitfieldOffset;
386 uint8 shift = ((channel % 8) * 2) + bitfieldOffset;
494 tgc->
ACT_TB.B.TB_TRIG = enabled ? 1 : 0;
510 resetMask = resetMask >> 1;
513 tgc->
GLB_CTRL.U = reg << IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH0_OFF;
519 uint32 regEnable, regReset;
524 tgc->
FUPD_CTRL.U |= regEnable | (regReset << 16);
530 uint32 regEnable, regReset;
541 Ifx_GTM_TOM_TGC0_ACT_TB act_tb;
544 act_tb.B.TBU_SEL = base;
545 act_tb.B.ACT_TB = value;
552 tgc->
GLB_CTRL.U = 1 << IFX_GTM_TOM_TGC0_GLB_CTRL_HOST_TRIG_OFF;