30 #include "IfxGtm_bf.h"
38 #define IFXGTM_ATOM_NUM_AGC_CHANNELS (8)
65 uint32 mask = enableMask | (disableMask << 16);
70 uint8 shift = (i * 2) + bitfieldOffset;
94 uint8 shift = (((
uint8)channel % 8) * 2) + bitfieldOffset;
117 agc->ENDIS_CTRL.U |= value;
118 agc->ENDIS_STAT.U |= value;
122 agc->ENDIS_CTRL.U |= value;
135 agc->OUTEN_CTRL.U |= value;
136 agc->OUTEN_STAT.U |= value;
140 agc->OUTEN_CTRL.U |= value;
157 value = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL0_OFF);
161 agc->ENDIS_CTRL.U = value;
162 agc->ENDIS_STAT.U = value;
166 agc->ENDIS_CTRL.U = value;
175 value = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL0_OFF);
179 agc->OUTEN_CTRL.U = value;
180 agc->OUTEN_STAT.U = value;
184 agc->OUTEN_CTRL.U = value;
191 agc->INT_TRIG.U = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG0_OFF);
197 agc->GLB_CTRL.U = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL0_OFF);
203 agc->ACT_TB.B.TB_TRIG = enabled ? 1 : 0;
219 resetMask = resetMask >> 1;
222 agc->GLB_CTRL.U = reg << IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH0_OFF;
228 uint32 regEnable, regReset;
233 agc->FUPD_CTRL.U |= regEnable | (regReset << 16);
239 uint32 regEnable, regReset;
241 regEnable = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL0_OFF);
242 regReset = IfxGtm_Atom_Agc_buildFeature(resetEnableMask, resetDisableMask, IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH0_OFF);
243 agc->FUPD_CTRL.U = regEnable | regReset;
249 Ifx_GTM_ATOM_AGC_ACT_TB act_tb;
251 act_tb.U = agc->ACT_TB.U;
252 act_tb.B.TBU_SEL = base;
253 act_tb.B.ACT_TB = value;
254 agc->ACT_TB.U = act_tb.U;
260 agc->GLB_CTRL.U = 1 << IFX_GTM_ATOM_AGC_GLB_CTRL_HOST_TRIG_OFF;
267 atomCh->IRQ_NOTIFY.B.CCU1TC = 1;
274 atomCh->IRQ_NOTIFY.B.CCU0TC = 1;
280 Ifx_GTM_ATOM_CH_CTRL_Bits ctrl = {
283 .RST_CCU0 = resetEvent,
289 atomCh->CTRL.B = ctrl;
308 clock = atomCh->CTRL.B.CLK_SRC;
317 return atomCh->CM1.U;
325 return (
volatile uint32 *)&atomCh->CM1;
333 return atomCh->CM0.U;
341 return (
volatile uint32 *)&atomCh->CM0;
350 result = atomCh->STAT.B.OL == 1;
358 return &MODULE_SRC.GTM.GTM[0].ATOM[atom][channel / 2];
364 return (
volatile uint32 *)((
uint32)&(atom->CH0.CN0.U) + channel * (offsetof(Ifx_GTM_ATOM, CH1) - offsetof(Ifx_GTM_ATOM, CH0)));
373 result = atomCh->IRQ_NOTIFY.B.CCU1TC != 0;
384 result = atomCh->IRQ_NOTIFY.B.CCU0TC != 0;
394 atomCh->IRQ_FORCINT.B.TRG_CCU1TC = 1;
402 atomCh->IRQ_FORCINT.B.TRG_CCU0TC = 1;
410 atomCh->CTRL.B.CLK_SRC = clock;
418 atomCh->CM0.U = compareZero;
419 atomCh->CM1.U = compareOne;
427 atomCh->CM1.U = compareOne;
435 atomCh->SR1.U = shadowOne;
443 atomCh->SR0.U = shadowZero;
444 atomCh->SR1.U = shadowOne;
452 atomCh->CM0.U = compareZero;
460 atomCh->SR0.U = shadowZero;
468 atomCh->CN0.U = value;
474 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
476 atomCh->CTRL.B.MODE = mode;
484 Ifx_GTM_ATOM_CH_IRQ_EN en;
486 en.U = atomCh->IRQ_EN.U;
490 atomCh->IRQ_MODE.B.IRQ_MODE = mode;
491 atomCh->IRQ_EN.U = en.U;
493 en.B.CCU0TC_IRQ_EN = interruptOnCompareZero ? 1 : 0;
494 en.B.CCU1TC_IRQ_EN = interruptOnCompareOne ? 1 : 0;
495 atomCh->IRQ_EN.U = en.U;
503 atomCh->CTRL.B.OSM = enabled ? 1 : 0;
511 atomCh->CTRL.B.RST_CCU0 = event;
527 atomCh->CTRL.B.TRIGOUT = trigger;