iLLD_TC27xD  1.0
IfxDma_cfg.h
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1 /**
2  * \file IfxDma_cfg.h
3  * \brief DMA on-chip implementation data
4  * \ingroup IfxLld_Dma
5  *
6  * \version iLLD_1_0_0_11_0
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Dma DMA
25  * \ingroup IfxLld
26  * \defgroup IfxLld_Dma_Impl Implementation
27  * \ingroup IfxLld_Dma
28  * \defgroup IfxLld_Dma_Std Standard Driver
29  * \ingroup IfxLld_Dma
30  */
31 
32 #ifndef IFXDMA_CFG_H
33 #define IFXDMA_CFG_H 1
34 
35 /******************************************************************************/
36 /*----------------------------------Includes----------------------------------*/
37 /******************************************************************************/
38 
39 #include "Cpu/Std/Ifx_Types.h"
40 
41 /******************************************************************************/
42 /*-----------------------------------Macros-----------------------------------*/
43 /******************************************************************************/
44 
45 /** \brief Number of channels
46  */
47 #define IFXDMA_NUM_CHANNELS 64
48 
49 /** \brief Error mask for move engine source error
50  */
51 #define IFXDMA_ERROR_S (IFX_DMA_BLK_CLRE_CSER_MSK << IFX_DMA_BLK_CLRE_CSER_OFF)
52 
53 /** \brief Error mask for move engine destination error
54  */
55 #define IFXDMA_ERROR_D (IFX_DMA_BLK_CLRE_CDER_MSK << IFX_DMA_BLK_CLRE_CDER_OFF)
56 
57 /** \brief Error mask for bus error on SPB
58  */
59 #define IFXDMA_ERROR_SPB (IFX_DMA_BLK_CLRE_CSPBER_MSK << IFX_DMA_BLK_CLRE_CSPBER_OFF)
60 
61 /** \brief Error mask for bus error on SRI
62  */
63 #define IFXDMA_ERROR_SRI (IFX_DMA_BLK_CLRE_CSRIER_MSK << IFX_DMA_BLK_CLRE_CSRIER_OFF)
64 
65 /** \brief Error mask for RAM error
66  */
67 #define IFXDMA_ERROR_RAM (IFX_DMA_BLK_CLRE_CRAMER_MSK << IFX_DMA_BLK_CLRE_CRAMER_OFF)
68 
69 /** \brief Error mask for SLL (safe linked list CRC checksum) error
70  */
71 #define IFXDMA_ERROR_SLL (IFX_DMA_BLK_CLRE_CSLLER_MSK << IFX_DMA_BLK_CLRE_CSLLER_OFF)
72 
73 /** \brief Error mask for DLL (failed linked list load) error
74  */
75 #define IFXDMA_ERROR_DLL (IFX_DMA_BLK_CLRE_CDLLER_MSK << IFX_DMA_BLK_CLRE_CDLLER_OFF)
76 
77 /******************************************************************************/
78 /*-------------------------------Enumerations---------------------------------*/
79 /******************************************************************************/
80 
81 /** \brief DMA channel resources definition
82  */
83 typedef enum
84 {
85  IfxDma_ChannelId_none = -1, /**< \brief None of the Ifx_DMA Channels */
86  IfxDma_ChannelId_0 = 0, /**< \brief Ifx_DMA Channel 0 */
87  IfxDma_ChannelId_1, /**< \brief Ifx_DMA Channel 1 */
88  IfxDma_ChannelId_2, /**< \brief Ifx_DMA Channel 2 */
89  IfxDma_ChannelId_3, /**< \brief Ifx_DMA Channel 3 */
90  IfxDma_ChannelId_4, /**< \brief Ifx_DMA Channel 4 */
91  IfxDma_ChannelId_5, /**< \brief Ifx_DMA Channel 5 */
92  IfxDma_ChannelId_6, /**< \brief Ifx_DMA Channel 6 */
93  IfxDma_ChannelId_7, /**< \brief Ifx_DMA Channel 7 */
94  IfxDma_ChannelId_8, /**< \brief Ifx_DMA Channel 8 */
95  IfxDma_ChannelId_9, /**< \brief Ifx_DMA Channel 9 */
96  IfxDma_ChannelId_10, /**< \brief Ifx_DMA Channel 10 */
97  IfxDma_ChannelId_11, /**< \brief Ifx_DMA Channel 11 */
98  IfxDma_ChannelId_12, /**< \brief Ifx_DMA Channel 12 */
99  IfxDma_ChannelId_13, /**< \brief Ifx_DMA Channel 13 */
100  IfxDma_ChannelId_14, /**< \brief Ifx_DMA Channel 14 */
101  IfxDma_ChannelId_15, /**< \brief Ifx_DMA Channel 15 */
102  IfxDma_ChannelId_16, /**< \brief Ifx_DMA Channel 16 */
103  IfxDma_ChannelId_17, /**< \brief Ifx_DMA Channel 17 */
104  IfxDma_ChannelId_18, /**< \brief Ifx_DMA Channel 18 */
105  IfxDma_ChannelId_19, /**< \brief Ifx_DMA Channel 19 */
106  IfxDma_ChannelId_20, /**< \brief Ifx_DMA Channel 20 */
107  IfxDma_ChannelId_21, /**< \brief Ifx_DMA Channel 21 */
108  IfxDma_ChannelId_22, /**< \brief Ifx_DMA Channel 22 */
109  IfxDma_ChannelId_23, /**< \brief Ifx_DMA Channel 23 */
110  IfxDma_ChannelId_24, /**< \brief Ifx_DMA Channel 24 */
111  IfxDma_ChannelId_25, /**< \brief Ifx_DMA Channel 25 */
112  IfxDma_ChannelId_26, /**< \brief Ifx_DMA Channel 26 */
113  IfxDma_ChannelId_27, /**< \brief Ifx_DMA Channel 27 */
114  IfxDma_ChannelId_28, /**< \brief Ifx_DMA Channel 28 */
115  IfxDma_ChannelId_29, /**< \brief Ifx_DMA Channel 29 */
116  IfxDma_ChannelId_30, /**< \brief Ifx_DMA Channel 30 */
117  IfxDma_ChannelId_31, /**< \brief Ifx_DMA Channel 31 */
118  IfxDma_ChannelId_32, /**< \brief Ifx_DMA Channel 32 */
119  IfxDma_ChannelId_33, /**< \brief Ifx_DMA Channel 33 */
120  IfxDma_ChannelId_34, /**< \brief Ifx_DMA Channel 34 */
121  IfxDma_ChannelId_35, /**< \brief Ifx_DMA Channel 35 */
122  IfxDma_ChannelId_36, /**< \brief Ifx_DMA Channel 36 */
123  IfxDma_ChannelId_37, /**< \brief Ifx_DMA Channel 37 */
124  IfxDma_ChannelId_38, /**< \brief Ifx_DMA Channel 38 */
125  IfxDma_ChannelId_39, /**< \brief Ifx_DMA Channel 39 */
126  IfxDma_ChannelId_40, /**< \brief Ifx_DMA Channel 40 */
127  IfxDma_ChannelId_41, /**< \brief Ifx_DMA Channel 41 */
128  IfxDma_ChannelId_42, /**< \brief Ifx_DMA Channel 42 */
129  IfxDma_ChannelId_43, /**< \brief Ifx_DMA Channel 43 */
130  IfxDma_ChannelId_44, /**< \brief Ifx_DMA Channel 44 */
131  IfxDma_ChannelId_45, /**< \brief Ifx_DMA Channel 45 */
132  IfxDma_ChannelId_46, /**< \brief Ifx_DMA Channel 46 */
133  IfxDma_ChannelId_47, /**< \brief Ifx_DMA Channel 47 */
134  IfxDma_ChannelId_48, /**< \brief Ifx_DMA Channel 48 */
135  IfxDma_ChannelId_49, /**< \brief Ifx_DMA Channel 49 */
136  IfxDma_ChannelId_50, /**< \brief Ifx_DMA Channel 50 */
137  IfxDma_ChannelId_51, /**< \brief Ifx_DMA Channel 51 */
138  IfxDma_ChannelId_52, /**< \brief Ifx_DMA Channel 52 */
139  IfxDma_ChannelId_53, /**< \brief Ifx_DMA Channel 53 */
140  IfxDma_ChannelId_54, /**< \brief Ifx_DMA Channel 54 */
141  IfxDma_ChannelId_55, /**< \brief Ifx_DMA Channel 55 */
142  IfxDma_ChannelId_56, /**< \brief Ifx_DMA Channel 56 */
143  IfxDma_ChannelId_57, /**< \brief Ifx_DMA Channel 57 */
144  IfxDma_ChannelId_58, /**< \brief Ifx_DMA Channel 58 */
145  IfxDma_ChannelId_59, /**< \brief Ifx_DMA Channel 59 */
146  IfxDma_ChannelId_60, /**< \brief Ifx_DMA Channel 60 */
147  IfxDma_ChannelId_61, /**< \brief Ifx_DMA Channel 61 */
148  IfxDma_ChannelId_62, /**< \brief Ifx_DMA Channel 62 */
149  IfxDma_ChannelId_63 /**< \brief Ifx_DMA Channel 63 */
150 } IfxDma_ChannelId;
151 
152 #endif /* IFXDMA_CFG_H */