iLLD_TC27xD  1.0
IfxCpu_CStart0.c
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1 /**
2  * \file IfxCpu_Cstart0.c
3  * \brief This file contains the Core startup sequence for Cpu0.
4  * \version iLLD_1_0_0_11_0
5  * \copyright Copyright (c) 2012 Infineon Technologies AG. All rights reserved.
6  *
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  */
24 /*******************************************************************************
25 ** Includes **
26 *******************************************************************************/
27 #include "Ifx_Cfg.h"
28 #ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
29 #include "Scu/Std/IfxScuWdt.h"
30 #include "Scu/Std/IfxScuCcu.h"
31 #include "Cpu/Std/IfxCpu.h"
32 #include "Cpu/CStart/IfxCpu_CStart.h"
33 #include "IfxScu_reg.h"
34 #include "IfxCpu_reg.h"
35 
36 /******************************************************************************/
37 /* Macros */
38 /******************************************************************************/
39 /** \brief Configuration for CpuX enable.
40  *
41  */
42 #ifndef IFX_CFG_CPU_CSTART_ENABLE_TRICORE0
43 # define IFX_CFG_CPU_CSTART_ENABLE_TRICORE0 (1) /**< Cpu0 enabled by default*/
44 #endif
45 #ifndef IFX_CFG_CPU_CSTART_ENABLE_TRICORE1
46 # define IFX_CFG_CPU_CSTART_ENABLE_TRICORE1 (1) /**< Cpu1 enabled by default*/
47 #endif
48 #ifndef IFX_CFG_CPU_CSTART_ENABLE_TRICORE2
49 # define IFX_CFG_CPU_CSTART_ENABLE_TRICORE2 (1) /**< Cpu2 enabled by default*/
50 #endif
51 
52 /** \brief Configuration for cache enable.
53  *
54  */
55 #ifndef IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_PCACHE
56 # define IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_PCACHE (1) /**< Program Cache enabled by default*/
57 #endif
58 #ifndef IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_DCACHE
59 # define IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_DCACHE (1) /**< Data Cache enabled by default*/
60 #endif
61 
62 #ifndef IFXCPU_CSTART_CCU_INIT_HOOK
63 #define IFXCPU_CSTART_CCU_INIT_HOOK() (void)IfxScuCcu_init(&IfxScuCcu_defaultClockConfig); /*The status returned by Ccu init is ignored */
64 #endif
65 
66 /*******************************************************************************
67 ** Imported Function Declarations **
68 *******************************************************************************/
69 IFXCOMPILER_COMMON_LINKER_SYMBOLS()
70 IFXCOMPILER_CORE_LINKER_SYMBOLS(0)
71 
72 IFX_EXTERN void core0_main(void);
73 #if defined(__TASKING__)
74 __asm("\t .extern core0_main");
75 #endif
76 
77 /*******************************************************************************
78 ** Private Constant Definitions **
79 *******************************************************************************/
80 #define IFXCSTART0_PSW_DEFAULT (0x00000980u)
81 #define IFXCSTART0_PCX_O_S_DEFAULT (0xfff00000u)
82 
83 /*********************************************************************************
84 * _start() - startup code
85 *********************************************************************************/
86 void _Core0_start(void)
87 {
88  uint32 pcxi;
89  uint16 cpuWdtPassword = IfxScuWdt_getCpuWatchdogPasswordInline(&MODULE_SCU.WDTCPU[0]);
90 
91  IFX_CFG_CPU_CSTART_PRE_C_INIT_HOOK(0); /*Test Stack, CSA and Cache */
92 
93  /* Load user stack pointer */
94  __setareg(sp, __USTACK(0));
95  __dsync();
96 
97  /* Set the PSW to its reset value in case of a warm start,clear PSW.IS */
98  __mtcr(CPU_PSW, IFXCSTART0_PSW_DEFAULT);
99 
100  /* Set the PCXS and PCXO to its reset value in case of a warm start */
101  pcxi = __mfcr(CPU_PCXI);
102  pcxi &= IFXCSTART0_PCX_O_S_DEFAULT; /*0xfff00000; */
103  __mtcr(CPU_PCXI, pcxi);
104 
105  /*enable/disable program cache depending on the configuration */
106  IfxCpu_setProgramCache(IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_PCACHE);
107 
108  /*enable/disable data cache depending on the configuration */
109  IfxCpu_setDataCache(IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_DCACHE);
110 
111  /* Clear the ENDINIT bit in the WDT_CON0 register, inline funtion */
112  IfxScuWdt_clearCpuEndinitInline(&MODULE_SCU.WDTCPU[0], cpuWdtPassword);
113 
114  /* Load Base Address of Trap Vector Table. */
115  __mtcr(CPU_BTV, (uint32)__TRAPTAB(0));
116 
117  /* Load Base Address of Interrupt Vector Table. we will do this later in the program */
118  __mtcr(CPU_BIV, (uint32)__INTTAB(0));
119 
120  /* Load interupt stack pointer. */
121  __mtcr(CPU_ISP, (uint32)__ISTACK(0));
122 
123  IfxScuWdt_setCpuEndinitInline(&MODULE_SCU.WDTCPU[0], cpuWdtPassword);
124 
125  /* initialize SDA base pointers */
126  __setareg(a0, __SDATA1(0));
127  __setareg(a1, __SDATA2(0));
128 
129  /* These to be un commented if A8 and A9 are required to be initialized */
130  __setareg(a8, __SDATA3(0));
131  __setareg(a9, __SDATA4(0));
132  /* Setup the context save area linked list. */
133 
134  IfxCpu_initCSA((uint32 *)__CSA(0), (uint32 *)__CSA_END(0)); /*Initialize the context save area for CPU0 */
135 
136  {
137  /*CPU and safety watchdogs are enabled by default, C initialization functions are not servicing the watchdogs */
138  uint16 safetyWdtPassword = IfxScuWdt_getSafetyWatchdogPassword();
139  IfxScuWdt_disableCpuWatchdog(cpuWdtPassword);
140  IfxScuWdt_disableSafetyWatchdog(safetyWdtPassword);
141 
142  Ifx_C_Init(); /*Initialization of C runtime variables */
143 
144  IfxScuWdt_enableCpuWatchdog(cpuWdtPassword);
145  IfxScuWdt_enableSafetyWatchdog(safetyWdtPassword);
146  }
147 
148  /*Initialize the clock system */
149  IFXCPU_CSTART_CCU_INIT_HOOK();
150 
151  /*Start remaining cores */
152 #if (IFX_CFG_CPU_CSTART_ENABLE_TRICORE1 != 0)
153  (void)IfxCpu_startCore(&MODULE_CPU1, (uint32)&_Core1_start); /*The status returned by function call is ignored */
154 #endif
155 #if (IFX_CFG_CPU_CSTART_ENABLE_TRICORE2 != 0)
156  (void)IfxCpu_startCore(&MODULE_CPU2, (uint32)&_Core2_start); /*The status returned by function call is ignored */
157 #endif
158 
159 #if (IFX_CFG_CPU_CSTART_ENABLE_TRICORE0 == 0)
160  IfxScuWdt_disableCpuWatchdog(cpuWdtPassword);
161  /*halt the CPU 0 if it is not needed to be enabled */
162  IfxCpu_setCoreMode(&MODULE_CPU0, IfxCpu_CoreMode_idle);
163 #endif
164 
165  /*Call main function of Cpu0 */
166  __non_return_call(core0_main);
167 }
168 
169 
170 /******************************************************************************
171  * reset vector address, user section to inform linker to locate the code at 0x8000 0020
172  *****************************************************************************/
173 #if defined(__GNUC__)
174 #pragma section
175 #pragma section ".start" x
176 #endif
177 #if defined(__TASKING__)
178 #pragma protect on
179 #pragma section code "start"
180 #endif
181 #if defined(__DCC__)
182 #pragma section CODE ".start" X
183 #endif
184 
185 void _START(void)
186 {
187  __non_return_call(_Core0_start);
188 }
189 
190 
191 /* reset the sections defined above, to normal region */
192 #if defined(__GNUC__)
193 #pragma section
194 #endif
195 #if defined(__TASKING__)
196 #pragma protect restore
197 #pragma section code restore
198 #endif
199 #if defined(__DCC__)
200 #pragma section CODE
201 #endif
202 
203 /*******************************************************************************
204 ** Boot Mode Headers **
205 *******************************************************************************/
206 /*Boot Mode Header 0 sections to inform linker to locate them at 0x8000 0000 */
207 #if defined(__GNUC__)
208 #pragma section
209 #pragma section ".bmhd_0" a
210 #endif
211 #if defined(__TASKING__)
212 #pragma protect on
213 #pragma section farrom "bmhd_0"
214 #endif
215 #if defined(__DCC__)
216 #pragma section CONST ".bmhd_0" R
217 #endif
218 /** \brief Boot Mode Header 0
219  * Boot mode header at memory location 0c8000 0000.
220  */
221 const uint32 BootModeHeader_0[] = {
222  0x00000000u, /* STADBM first user code at 0x8000 0020h */
223  0xb3590070u, /* BMI = 0070h BMHDID = B359h */
224  0x00000000u, /* ChkStart */
225  0x00000000u, /* ChkEnd */
226  0x00000000u, /* CRCrange */
227  0x00000000u, /* !CRCrange */
228  0x791eb864u, /* CRChead */
229  0x86e1479bu /* !CRChead */
230 };
231 
232 /*reset the sections defined above */
233 #if defined(__GNUC__)
234 #pragma section
235 #endif
236 #if defined(__TASKING__)
237 #pragma protect restore
238 #pragma section farrom restore
239 #endif
240 #if defined(__DCC__)
241 #pragma section CONST
242 #endif
243 
244 #ifndef IFX_CFG_CPUCSTART_BMI01_NOT_NEEDED
245 /*Boot Mode Header 1 sections to inform linker to locate them at 0x8002 0000 */
246 #if defined(__GNUC__)
247 #pragma section
248 #pragma section ".bmhd_1" a
249 #endif
250 #if defined(__TASKING__)
251 #pragma protect on
252 #pragma section farrom "bmhd_1"
253 #endif
254 #if defined(__DCC__)
255 #pragma section CONST ".bmhd_1" R
256 #endif
257 
258 /** \brief Boot Mode Header 1
259  * Boot mode header at memory location 0c8002 0000.
260  */
261 const uint32 BootModeHeader_1[] = {
262  0x00000000u, /* STADBM first user code at 0x8000 0020h */
263  0xB3590070u, /* BMI = 0070h BMHDID = B359h */
264  0x00000000u, /* ChkStart */
265  0x00000000u, /* ChkEnd */
266  0x00000000u, /* CRCrange */
267  0x00000000u, /* !CRCrange */
268  0x791eb864u, /* CRChead */
269  0x86e1479bu /* !CRChead */
270 };
271 
272 /*reset the sections defined above */
273 #if defined(__GNUC__)
274 #pragma section
275 #endif
276 #if defined(__TASKING__)
277 #pragma protect restore
278 #pragma section farrom restore
279 #endif
280 #if defined(__DCC__)
281 #pragma section CONST
282 #endif
283 #endif /*IFX_CFG_CPUCSTART_BMI01_NOT_NEEDED*/
284 
285 #endif /*#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER */