iLLD_TC27xC
1.0
iLLD_TC27xC
IFX Low Level Drivers
Modules
Data Structures
Files
File List
Assert.c
Assert.h
Bsp.c
Bsp.h
CompilerDcc.c
CompilerDcc.h
CompilerGnuc.c
CompilerGnuc.h
Compilers.h
CompilerTasking.c
CompilerTasking.h
Icu.h
Ifx_Assert.h
Ifx_CircularBuffer.asm.c
Ifx_CircularBuffer.c
Ifx_CircularBuffer.h
Ifx_Console.c
Ifx_Console.h
Ifx_DateTime.c
Ifx_DateTime.h
Ifx_Fifo.c
Ifx_Fifo.h
Ifx_GlobalResources.c
Ifx_GlobalResources.h
Ifx_InternalMux.c
Ifx_InternalMux.h
Ifx_LowPassPt1.c
Ifx_LowPassPt1.h
Ifx_Shell.c
Ifx_Shell.h
Ifx_Types.h
Ifx_TypesDcc.h
Ifx_TypesGnuc.h
Ifx_TypesTasking.h
IfxAsclin.c
IfxAsclin.h
IfxAsclin_Asc.c
IfxAsclin_Asc.h
IfxAsclin_cfg.h
IfxAsclin_Lin.c
IfxAsclin_Lin.h
IfxAsclin_PinMap.c
IfxAsclin_PinMap.h
IfxAsclin_Spi.c
IfxAsclin_Spi.h
IfxCcu6.c
IfxCcu6.h
IfxCcu6_cfg.c
IfxCcu6_cfg.h
IfxCcu6_Icu.c
IfxCcu6_Icu.h
IfxCcu6_PinMap.c
IfxCcu6_PinMap.h
IfxCcu6_PwmBc.c
IfxCcu6_PwmBc.h
IfxCcu6_PwmHl.c
IfxCcu6_PwmHl.h
IfxCcu6_Timer.c
IfxCcu6_Timer.h
IfxCcu6_TimerWithTrigger.c
IfxCcu6_TimerWithTrigger.h
IfxCcu6_TPwm.c
IfxCcu6_TPwm.h
IfxCif.c
IfxCif.h
IfxCif_Cam.c
IfxCif_Cam.h
IfxCif_cfg.c
IfxCif_cfg.h
IfxCif_PinMap.c
IfxCif_PinMap.h
IfxCpu.c
IfxCpu.h
IfxCpu_cfg.c
IfxCpu_cfg.h
IfxCpu_CStart.h
IfxCpu_CStart0.c
IfxCpu_CStart1.c
IfxCpu_CStart2.c
IfxCpu_Intrinsics.h
IfxCpu_IntrinsicsDcc.h
IfxCpu_IntrinsicsGnuc.h
IfxCpu_IntrinsicsTasking.h
IfxCpu_Irq.c
IfxCpu_Irq.h
IfxCpu_Trap.c
IfxCpu_Trap.h
IfxDma.c
IfxDma.h
IfxDma_cfg.c
IfxDma_cfg.h
IfxDma_Dma.c
IfxDma_Dma.h
IfxDsadc.c
IfxDsadc.h
IfxDsadc_cfg.h
IfxDsadc_Dsadc.c
IfxDsadc_Dsadc.h
IfxDsadc_PinMap.c
IfxDsadc_PinMap.h
IfxDts.c
IfxDts.h
IfxDts_cfg.h
IfxDts_Dts.c
IfxDts_Dts.h
IfxEmem.c
IfxEmem.h
IfxEmem_cfg.h
IfxEray.c
IfxEray.h
IfxEray_cfg.h
IfxEray_Eray.c
IfxEray_Eray.h
IfxEray_PinMap.c
IfxEray_PinMap.h
IfxEth.c
IfxEth.h
IfxEth_cfg.h
IfxEth_Phy_Pef7071.c
IfxEth_Phy_Pef7071.h
IfxEth_PinMap.c
IfxEth_PinMap.h
IfxFce.c
IfxFce.h
IfxFce_cfg.h
IfxFce_Crc.c
IfxFce_Crc.h
IfxFlash.c
IfxFlash.h
IfxFlash_cfg.c
IfxFlash_cfg.h
IfxGlobal_cfg.h
IfxGpt12.c
IfxGpt12.h
IfxGpt12_cfg.h
IfxGpt12_IncrEnc.c
IfxGpt12_IncrEnc.h
IfxGpt12_PinMap.c
IfxGpt12_PinMap.h
IfxGtm.c
IfxGtm.h
IfxGtm_Atom.c
IfxGtm_Atom.h
IfxGtm_Atom_Pwm.c
IfxGtm_Atom_Pwm.h
IfxGtm_Atom_PwmHl.c
IfxGtm_Atom_PwmHl.h
IfxGtm_Atom_Timer.c
IfxGtm_Atom_Timer.h
IfxGtm_cfg.h
IfxGtm_Cmu.c
IfxGtm_Cmu.h
IfxGtm_Dpll.c
IfxGtm_Dpll.h
IfxGtm_PinMap.c
IfxGtm_PinMap.h
IfxGtm_Tbu.c
IfxGtm_Tbu.h
IfxGtm_Tim.c
IfxGtm_Tim.h
IfxGtm_Tom.c
IfxGtm_Tom.h
IfxGtm_Tom_Pwm.c
IfxGtm_Tom_Pwm.h
IfxGtm_Tom_PwmHl.c
IfxGtm_Tom_PwmHl.h
IfxGtm_Tom_Timer.c
IfxGtm_Tom_Timer.h
IfxGtm_Trig.c
IfxGtm_Trig.h
IfxHssl.c
IfxHssl.h
IfxHssl_cfg.h
IfxHssl_Hssl.c
IfxHssl_Hssl.h
IfxI2c.c
IfxI2c.h
IfxI2c_cfg.h
IfxI2c_I2c.c
IfxI2c_I2c.h
IfxI2c_PinMap.c
IfxI2c_PinMap.h
IfxIom.c
IfxIom.h
IfxIom_cfg.h
IfxIom_Iom.c
IfxIom_Iom.h
IfxLldVersion.h
IfxMsc.c
IfxMsc.h
IfxMsc_cfg.c
IfxMsc_cfg.h
IfxMsc_Msc.c
IfxMsc_Msc.h
IfxMsc_PinMap.c
IfxMsc_PinMap.h
IfxMtu.c
IfxMtu.h
IfxMtu_cfg.c
IfxMtu_cfg.h
IfxMultican.c
IfxMultican.h
IfxMultican_Can.c
IfxMultican_Can.h
IfxMultican_cfg.c
IfxMultican_cfg.h
IfxMultican_PinMap.c
IfxMultican_PinMap.h
IfxPort.c
IfxPort.h
IfxPort_cfg.c
IfxPort_cfg.h
IfxPort_Io.c
IfxPort_Io.h
IfxPort_PinMap.c
IfxPort_PinMap.h
IfxPsi5.c
IfxPsi5.h
IfxPsi5_cfg.c
IfxPsi5_cfg.h
IfxPsi5_PinMap.c
IfxPsi5_PinMap.h
IfxPsi5_Psi5.c
IfxPsi5_Psi5.h
IfxPsi5s.c
IfxPsi5s.h
IfxPsi5s_cfg.h
IfxPsi5s_PinMap.c
IfxPsi5s_PinMap.h
IfxPsi5s_Psi5s.c
IfxPsi5s_Psi5s.h
IfxQspi.c
IfxQspi.h
IfxQspi_cfg.c
IfxQspi_cfg.h
IfxQspi_PinMap.c
IfxQspi_PinMap.h
IfxQspi_SpiMaster.c
IfxQspi_SpiMaster.h
IfxQspi_SpiSlave.c
IfxQspi_SpiSlave.h
IfxScu_cfg.c
IfxScu_cfg.h
IfxScu_PinMap.c
IfxScu_PinMap.h
IfxScuCcu.c
IfxScuCcu.h
IfxScuEru.c
IfxScuEru.h
IfxScuWdt.asm.h
IfxScuWdt.c
IfxScuWdt.h
IfxSent.c
IfxSent.h
IfxSent_cfg.c
IfxSent_cfg.h
IfxSent_PinMap.c
IfxSent_PinMap.h
IfxSent_Sent.c
IfxSent_Sent.h
IfxSmu_PinMap.c
IfxSmu_PinMap.h
IfxSrc.c
IfxSrc.h
IfxSrc_cfg.c
IfxSrc_cfg.h
IfxStdIf.h
IfxStdIf_DPipe.c
IfxStdIf_DPipe.h
IfxStdIf_Pos.c
IfxStdIf_Pos.h
IfxStdIf_PwmHl.c
IfxStdIf_PwmHl.h
IfxStdIf_Timer.c
IfxStdIf_Timer.h
IfxStm.c
IfxStm.h
IfxStm_cfg.c
IfxStm_cfg.h
IfxVadc.c
IfxVadc.h
IfxVadc_Adc.c
IfxVadc_Adc.h
IfxVadc_cfg.c
IfxVadc_cfg.h
IfxVadc_PinMap.c
IfxVadc_PinMap.h
lld_api.c
lld_codingRules.c
lld_codingRules_codeFormating.c
lld_codingRules_commonApis.c
lld_codingRules_if.c
lld_conventions.c
lld_conventionsDoxygen.c
lld_dosanddont.c
lld_dosanddont_enumUsage.c
lld_dosanddont_namingConvention.c
lld_dosanddont_optimisation.c
lld_filesAndConfig.c
lld_structure.c
lld_versioning.c
mainpage.c
Platform_Types.h
PwmHl.h
SpiIf.c
SpiIf.h
Timer.h
TPwm.h
Globals
IfxPsi5.h
Go to the documentation of this file.
1
/**
2
* \file IfxPsi5.h
3
* \brief PSI5 basic functionality
4
* \ingroup IfxLld_Psi5
5
*
6
* \version iLLD_1_0_0_11_0
7
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8
*
9
*
10
* IMPORTANT NOTICE
11
*
12
*
13
* Infineon Technologies AG (Infineon) is supplying this file for use
14
* exclusively with Infineon's microcontroller products. This file can be freely
15
* distributed within development tools that are supporting such microcontroller
16
* products.
17
*
18
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23
*
24
* \defgroup IfxLld_Psi5_Std_Enumerations Enumerations
25
* \ingroup IfxLld_Psi5_Std
26
* \defgroup IfxLld_Psi5_Std_Channel Channel Status Functions
27
* \ingroup IfxLld_Psi5_Std
28
* \defgroup IfxLld_Psi5_Std_IO IO Pin Configuration Functions
29
* \ingroup IfxLld_Psi5_Std
30
* \defgroup IfxLld_Psi5_Std_Interrupt Interrupt configuration function
31
* \ingroup IfxLld_Psi5_Std
32
*/
33
34
#ifndef IFXPSI5_H
35
#define IFXPSI5_H 1
36
37
/******************************************************************************/
38
/*----------------------------------Includes----------------------------------*/
39
/******************************************************************************/
40
41
#include "
_Impl/IfxPsi5_cfg.h
"
42
#include "
_PinMap/IfxPsi5_PinMap.h
"
43
#include "IfxPsi5_reg.h"
44
#include "
Scu/Std/IfxScuWdt.h
"
45
#include "
Cpu/Std/IfxCpu_Intrinsics.h
"
46
#include "
Src/Std/IfxSrc.h
"
47
48
/******************************************************************************/
49
/*--------------------------------Enumerations--------------------------------*/
50
/******************************************************************************/
51
52
/** \addtogroup IfxLld_Psi5_Std_Enumerations
53
* \{ */
54
/** \brief MODULE_PSI5.IOCRx.ALTI(x = 0,1,2),Alternate input selection
55
*/
56
typedef
enum
57
{
58
IfxPsi5_AlternateInput_0
= 0,
/**< \brief Alternate Input 0 */
59
IfxPsi5_AlternateInput_1
,
/**< \brief Alternate Input 1 */
60
IfxPsi5_AlternateInput_2
,
/**< \brief Alternate Input 2 */
61
IfxPsi5_AlternateInput_3
/**< \brief Alternate Input 3 */
62
}
IfxPsi5_AlternateInput
;
63
64
/** \brief MODULE_PSI5.RCRCx.BRS(x = 0,1,2),Baud rate selection
65
*/
66
typedef
enum
67
{
68
IfxPsi5_BaudRate_125
= 0,
/**< \brief Slow 125 kHz clock */
69
IfxPsi5_BaudRate_189
= 1
/**< \brief Fast 189 kHz clock */
70
}
IfxPsi5_BaudRate
;
71
72
/** \brief MODULE_PSI5.RCRBx.CRCy(x = 0,1,2; y=0,1,2,3,4,5),CRC or parity selection
73
*/
74
typedef
enum
75
{
76
IfxPsi5_CRCorParity_parity
= 0,
/**< \brief parity selection */
77
IfxPsi5_CRCorParity_crc
= 1
/**< \brief CRC selection */
78
}
IfxPsi5_CRCorParity
;
79
80
/** \brief Clock type
81
*/
82
typedef
enum
83
{
84
IfxPsi5_ClockType_fracDiv
= 0,
/**< \brief Fractional Divide clock */
85
IfxPsi5_ClockType_slowClock_125
= 1,
/**< \brief Slow 125 kHz clock */
86
IfxPsi5_ClockType_fastClock_189
= 2,
/**< \brief Fast 189 kHz clock */
87
IfxPsi5_ClockType_timeStamp
= 3
/**< \brief Timestamp clock */
88
}
IfxPsi5_ClockType
;
89
90
/** \brief MODULE_PSI5.IOCRx.DEPTH(x = 0,1,2),Digital input filter depth
91
*/
92
typedef
enum
93
{
94
IfxPsi5_DigitalInputFilterDepth_0
= 0,
/**< \brief Digital input filter depth is 0 */
95
IfxPsi5_DigitalInputFilterDepth_1
,
/**< \brief Digital input filter depth is 1 */
96
IfxPsi5_DigitalInputFilterDepth_2
,
/**< \brief Digital input filter depth is 2 */
97
IfxPsi5_DigitalInputFilterDepth_3
,
/**< \brief Digital input filter depth is 3 */
98
IfxPsi5_DigitalInputFilterDepth_4
,
/**< \brief Digital input filter depth is 4 */
99
IfxPsi5_DigitalInputFilterDepth_5
,
/**< \brief Digital input filter depth is 5 */
100
IfxPsi5_DigitalInputFilterDepth_6
,
/**< \brief Digital input filter depth is 6 */
101
IfxPsi5_DigitalInputFilterDepth_7
,
/**< \brief Digital input filter depth is 7 */
102
IfxPsi5_DigitalInputFilterDepth_8
,
/**< \brief Digital input filter depth is 8 */
103
IfxPsi5_DigitalInputFilterDepth_9
,
/**< \brief Digital input filter depth is 9 */
104
IfxPsi5_DigitalInputFilterDepth_10
,
/**< \brief Digital input filter depth is 10 */
105
IfxPsi5_DigitalInputFilterDepth_11
,
/**< \brief Digital input filter depth is 11 */
106
IfxPsi5_DigitalInputFilterDepth_12
,
/**< \brief Digital input filter depth is 12 */
107
IfxPsi5_DigitalInputFilterDepth_13
,
/**< \brief Digital input filter depth is 13 */
108
IfxPsi5_DigitalInputFilterDepth_14
,
/**< \brief Digital input filter depth is 14 */
109
IfxPsi5_DigitalInputFilterDepth_15
/**< \brief Digital input filter depth is 15 */
110
}
IfxPsi5_DigitalInputFilterDepth
;
111
112
/** \brief MODULE_PSI5.FDR.DM,Divider mode
113
*/
114
typedef
enum
115
{
116
IfxPsi5_DividerMode_spb
= 0,
/**< \brief divider mode is off */
117
IfxPsi5_DividerMode_normal
= 1,
/**< \brief divider mode is normal */
118
IfxPsi5_DividerMode_fractional
= 2,
/**< \brief divider mode is fractional */
119
IfxPsi5_DividerMode_off
= 3
/**< \brief divider mode is off */
120
}
IfxPsi5_DividerMode
;
121
122
/** \brief MODULE_PSI5.RCRBx.FECy(x = 0,1,2; y=0,1,2,3,4,5),Frame expectation control
123
*/
124
typedef
enum
125
{
126
IfxPsi5_FrameExpectation_notExpected
= 0,
/**< \brief No frame is expected */
127
IfxPsi5_FrameExpectation_expected
= 1
/**< \brief Frame is expected */
128
}
IfxPsi5_FrameExpectation
;
129
130
/** \brief MODULE_PSI5.RCRBx.MSGy(x = 0,1,2; y=0,1,2,3,4,5),Messaging bits presence
131
*/
132
typedef
enum
133
{
134
IfxPsi5_MessagingBits_absent
= 0,
/**< \brief No messaging bits */
135
IfxPsi5_MessagingBits_present
= 1
/**< \brief 2 messaging bits */
136
}
IfxPsi5_MessagingBits
;
137
138
/** \brief MODULE_PSI5.RCRCx.TSR(x = 0,1,2),Timestamp select for receive data registers
139
*/
140
typedef
enum
141
{
142
IfxPsi5_ReceiveDataRegisterTimestamp_pulse
= 0,
/**< \brief Pulse based timestamp SPTSC to be stored in RDRHC */
143
IfxPsi5_ReceiveDataRegisterTimestamp_frame
= 1
/**< \brief Start of frame based timestamp SPTSC to be stored in RDRHC */
144
}
IfxPsi5_ReceiveDataRegisterTimestamp
;
145
146
/** \brief MODULE_PSI5.RDRHx.SC(x = 0-2),Slot Id
147
*/
148
typedef
enum
149
{
150
IfxPsi5_Slot_0
= 0,
/**< \brief slot 0 */
151
IfxPsi5_Slot_1
,
/**< \brief slot 1 */
152
IfxPsi5_Slot_2
,
/**< \brief slot 2 */
153
IfxPsi5_Slot_3
,
/**< \brief slot 3 */
154
IfxPsi5_Slot_4
,
/**< \brief slot 4 */
155
IfxPsi5_Slot_5
/**< \brief slot 5 */
156
}
IfxPsi5_Slot
;
157
158
/** \brief MODULE_PSI5.PGCx.TBS(x = 0,1,2),Time base
159
*/
160
typedef
enum
161
{
162
IfxPsi5_TimeBase_internal
= 0,
/**< \brief Internal time stamp clock */
163
IfxPsi5_TimeBase_external
= 1
/**< \brief External GTM inputs */
164
}
IfxPsi5_TimeBase
;
165
166
/** \brief MODULE_PSI5.RCRCx.TSP(x = 0,1,2),MODULE_PSI5.RCRCx.TSF(x = 0,1,2)Timestamp register type
167
*/
168
typedef
enum
169
{
170
IfxPsi5_TimestampRegister_a
= 0,
/**< \brief Timestamp register A */
171
IfxPsi5_TimestampRegister_b
= 1,
/**< \brief Timestamp register B */
172
IfxPsi5_TimestampRegister_c
= 2
/**< \brief Timestamp register C */
173
}
IfxPsi5_TimestampRegister
;
174
175
/** \brief MODULE_PSI5.PGCx.ETS(x = 0,1,2),Trigger Id
176
*/
177
typedef
enum
178
{
179
IfxPsi5_Trigger_0
= 0,
/**< \brief trigger 0 */
180
IfxPsi5_Trigger_1
,
/**< \brief trigger 1 */
181
IfxPsi5_Trigger_2
,
/**< \brief trigger 2 */
182
IfxPsi5_Trigger_3
,
/**< \brief trigger 3 */
183
IfxPsi5_Trigger_4
,
/**< \brief trigger 4 */
184
IfxPsi5_Trigger_5
/**< \brief trigger 5 */
185
}
IfxPsi5_Trigger
;
186
187
/** \brief Trigger type
188
*/
189
typedef
enum
190
{
191
IfxPsi5_TriggerType_periodic
= 0,
/**< \brief Periodic trigger */
192
IfxPsi5_TriggerType_external
= 1,
/**< \brief External trigger */
193
IfxPsi5_TriggerType_bypass
= 2
/**< \brief Bypassed trigger */
194
}
IfxPsi5_TriggerType
;
195
196
/** \brief MODULE_PSI5.RCRBx.VBSy(x = 0,1,2; y=0,1,2,3,4,5),Verbose mode
197
*/
198
typedef
enum
199
{
200
IfxPsi5_Verbose_off
= 0,
/**< \brief Verbose mode is turned off */
201
IfxPsi5_Verbose_on
= 1
/**< \brief Verbose mode is turned on */
202
}
IfxPsi5_Verbose
;
203
204
/** \} */
205
206
/** \addtogroup IfxLld_Psi5_Std_Channel
207
* \{ */
208
209
/******************************************************************************/
210
/*-------------------------Inline Function Prototypes-------------------------*/
211
/******************************************************************************/
212
213
/** \brief access function to get the CRCI status register contents for a channel
214
* \param psi5 pointer to the PSI5 register space
215
* \param channel channel Id
216
* \return Crci status register contents
217
*/
218
IFX_INLINE
uint32
IfxPsi5_getStatusCrci
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel);
219
220
/** \brief access function to get the MEI status register contents for a channel
221
* \param psi5 pointer to the PSI5 register space
222
* \param channel channel Id
223
* \return Mei status register contents
224
*/
225
IFX_INLINE
uint32
IfxPsi5_getStatusMei
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel);
226
227
/** \brief access function to get the NBI status register contents for a channel
228
* \param psi5 pointer to the PSI5 register space
229
* \param channel channel Id
230
* \return Nbi status register contents
231
*/
232
IFX_INLINE
uint32
IfxPsi5_getStatusNbi
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel);
233
234
/** \brief access function to get the NFI status register contents for a channel
235
* \param psi5 pointer to the PSI5 register space
236
* \param channel channel Id
237
* \return Nfi status register contents
238
*/
239
IFX_INLINE
uint32
IfxPsi5_getStatusNfi
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel);
240
241
/** \brief access function to get the RDI status register contents for a channel
242
* \param psi5 pointer to the PSI5 register space
243
* \param channel channel Id
244
* \return Rdi status register contents
245
*/
246
IFX_INLINE
uint32
IfxPsi5_getStatusRdi
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel);
247
248
/** \brief access function to get the RMI status register contents for a channel
249
* \param psi5 pointer to the PSI5 register space
250
* \param channel channel Id
251
* \return Rmi status register contents
252
*/
253
IFX_INLINE
uint32
IfxPsi5_getStatusRmi
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel);
254
255
/** \brief access function to get the RSI status register contents for a channel
256
* \param psi5 pointer to the PSI5 register space
257
* \param channel channel Id
258
* \return Rsi status register contents
259
*/
260
IFX_INLINE
uint32
IfxPsi5_getStatusRsi
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel);
261
262
/** \brief access function to get the TEI status register contents for a channel
263
* \param psi5 pointer to the PSI5 register space
264
* \param channel channel Id
265
* \return Tei status register contents
266
*/
267
IFX_INLINE
uint32
IfxPsi5_getStatusTei
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel);
268
269
/******************************************************************************/
270
/*-------------------------Global Function Prototypes-------------------------*/
271
/******************************************************************************/
272
273
/** \brief resets PSI5 kernel
274
* \param psi5 pointer to PSI5 registers
275
* \return None
276
*/
277
IFX_EXTERN
void
IfxPsi5_resetModule
(Ifx_PSI5 *psi5);
278
279
/** \} */
280
281
/** \addtogroup IfxLld_Psi5_Std_IO
282
* \{ */
283
284
/******************************************************************************/
285
/*-------------------------Inline Function Prototypes-------------------------*/
286
/******************************************************************************/
287
288
/** \brief Initializes a RX input
289
* \param rx the RX Pin which should be configured
290
* \param inputMode pin input mode which should be configured
291
* \return None
292
*/
293
IFX_INLINE
void
IfxPsi5_initRxPin
(
const
IfxPsi5_Rx_In
*rx,
IfxPort_InputMode
inputMode);
294
295
/** \brief Initializes a TX output
296
* \param tx the TX Pin which should be configured
297
* \param outputMode the pin output mode which should be configured
298
* \param padDriver the pad driver mode which should be configured
299
* \return None
300
*/
301
IFX_INLINE
void
IfxPsi5_initTxPin
(
const
IfxPsi5_Tx_Out
*tx,
IfxPort_OutputMode
outputMode,
IfxPort_PadDriver
padDriver);
302
303
/** \brief Sets the alternate RX input
304
* \param psi5Ch pointer to the PSI5 channel register space
305
* \param alternateInput Alternate RX input selection
306
* \return None
307
*/
308
IFX_INLINE
void
IfxPsi5_setRxInput
(Ifx_PSI5_CH *psi5Ch,
IfxPsi5_AlternateInput
alternateInput);
309
310
/** \} */
311
312
/******************************************************************************/
313
/*---------------------Inline Function Implementations------------------------*/
314
/******************************************************************************/
315
316
IFX_INLINE
uint32
IfxPsi5_getStatusCrci
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel)
317
{
318
return
psi5->CRCIOV[channel].U;
319
}
320
321
322
IFX_INLINE
uint32
IfxPsi5_getStatusMei
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel)
323
{
324
return
psi5->MEIOV[channel].U;
325
}
326
327
328
IFX_INLINE
uint32
IfxPsi5_getStatusNbi
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel)
329
{
330
return
psi5->NBIOV[channel].U;
331
}
332
333
334
IFX_INLINE
uint32
IfxPsi5_getStatusNfi
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel)
335
{
336
return
psi5->NFIOV[channel].U;
337
}
338
339
340
IFX_INLINE
uint32
IfxPsi5_getStatusRdi
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel)
341
{
342
return
psi5->RDIOV[channel].U;
343
}
344
345
346
IFX_INLINE
uint32
IfxPsi5_getStatusRmi
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel)
347
{
348
return
psi5->RMIOV[channel].U;
349
}
350
351
352
IFX_INLINE
uint32
IfxPsi5_getStatusRsi
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel)
353
{
354
return
psi5->RSIOV[channel].U;
355
}
356
357
358
IFX_INLINE
uint32
IfxPsi5_getStatusTei
(Ifx_PSI5 *psi5,
IfxPsi5_ChannelId
channel)
359
{
360
return
psi5->TEIOV[channel].U;
361
}
362
363
364
IFX_INLINE
void
IfxPsi5_initRxPin
(
const
IfxPsi5_Rx_In
*rx,
IfxPort_InputMode
inputMode)
365
{
366
IfxPort_setPinModeInput
(rx->
pin
.
port
, rx->
pin
.
pinIndex
, inputMode);
367
Ifx_PSI5 *psi5 = rx->
module
;
368
Ifx_PSI5_CH *psi5Ch = &psi5->CH[rx->
channelId
];
369
IfxPsi5_setRxInput
(psi5Ch, (
IfxPsi5_AlternateInput
)rx->
select
);
370
}
371
372
373
IFX_INLINE
void
IfxPsi5_initTxPin
(
const
IfxPsi5_Tx_Out
*tx,
IfxPort_OutputMode
outputMode,
IfxPort_PadDriver
padDriver)
374
{
375
IfxPort_setPinModeOutput
(tx->
pin
.
port
, tx->
pin
.
pinIndex
, outputMode, tx->
select
);
376
IfxPort_setPinPadDriver
(tx->
pin
.
port
, tx->
pin
.
pinIndex
, padDriver);
377
}
378
379
380
IFX_INLINE
void
IfxPsi5_setRxInput
(Ifx_PSI5_CH *psi5Ch,
IfxPsi5_AlternateInput
alternateInput)
381
{
382
uint16
passwd =
IfxScuWdt_getCpuWatchdogPassword
();
383
IfxScuWdt_clearCpuEndinit
(passwd);
384
psi5Ch->IOCR.B.ALTI = alternateInput;
385
IfxScuWdt_setCpuEndinit
(passwd);
386
}
387
388
389
#endif
/* IFXPSI5_H */
home
mclld
Libraries
release
iLLD_1_0_0_11_0
src
ifx
TC27xC
Psi5
Std
IfxPsi5.h
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