iLLD_TC27xC  1.0
IfxMsc.c
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1 /**
2  * \file IfxMsc.c
3  * \brief MSC basic functionality
4  *
5  * \version iLLD_1_0_0_11_0
6  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  */
24 
25 /******************************************************************************/
26 /*----------------------------------Includes----------------------------------*/
27 /******************************************************************************/
28 
29 #include "IfxMsc.h"
30 
31 /******************************************************************************/
32 /*-------------------------Function Implementations---------------------------*/
33 /******************************************************************************/
34 
35 void IfxMsc_clearDataFrameInterruptFlag(Ifx_MSC *msc)
36 {
37  /* Data Frame Interrupt Clear */
38  msc->ISC.B.CDEDI = 1;
39 }
40 
41 
42 void IfxMsc_clearReset(Ifx_MSC *msc)
43 {
44  uint16 passwd = IfxScuWdt_getCpuWatchdogPassword();
45 
46  IfxScuWdt_clearCpuEndinit(passwd);
47 
48  if (msc->KRST0.B.RSTSTAT == 1)
49  {
50  msc->KRSTCLR.B.CLR = 1; /* Clear Kernel reset status bit */
51  }
52 
53  IfxScuWdt_setCpuEndinit(passwd);
54 }
55 
56 
57 uint32 IfxMsc_downstreamAbraBaudCalculator(uint32 baud)
58 {
59  uint32 fsys = IfxScuCcu_getSpbFrequency();
60  uint32 ndd = 0;
61 
62  /* DSTE.NDD = fsys / 2*BR */
63 
64  ndd = fsys / (2 * baud);
65 
66  return ndd - 1;
67 }
68 
69 
70 void IfxMsc_enableModule(Ifx_MSC *msc)
71 {
72  /* Disable module disable bit */
73  msc->CLC.U = 0;
74 }
75 
76 
77 boolean IfxMsc_getActiveDataFrameStatus(Ifx_MSC *msc)
78 {
79  return msc->DSS.B.DFA;
80 }
81 
82 
83 boolean IfxMsc_getDataFrameInterruptFlag(Ifx_MSC *msc)
84 {
85  boolean flag = 0;
86 
87  flag = msc->ISR.B.DEDI;
88 
89  return flag;
90 }
91 
92 
93 void IfxMsc_resetModule(Ifx_MSC *msc)
94 {
95  uint16 passwd = IfxScuWdt_getCpuWatchdogPassword();
96 
97  IfxScuWdt_clearCpuEndinit(passwd);
98 
99  /* Reset kernel */
100  msc->KRST1.B.RST = 1;
101  msc->KRST0.B.RST = 1; /* Only if both Kernel reset bits are set a reset is executed */
102 
103  while (msc->KRST0.B.RSTSTAT == 0) /* Wait until reset is executed */
104 
105  {}
106 
107  /* TODO Check if CLC enable is required */
108  //msc->KRSTCLR.B.CLR = 1; /* Clear Kernel reset status bit */
109 
110  IfxScuWdt_setCpuEndinit(passwd);
111 }
112 
113 
114 uint64 IfxMsc_upstreamFractionalBaudCalculator(Ifx_MSC *msc, uint32 baud)
115 {
116  float32 fsys = IfxScuCcu_getSpbFrequency();
117  uint64 step = 0;
118  uint32 df = 1;
119 
120  /* FDR.STEP = DF*BR*1024 / fsys */
121 
122  if (msc->USR.B.URR != 0)
123  {
124  df = (msc->USR.B.URR + 1);
125  }
126  else
127  {
128  df = 0;
129  }
130 
131  step = (uint64)((uint64)((df * baud) * 1024)) / fsys;
132 
133  return step;
134 }
135 
136 
137 uint32 IfxMsc_upstreamNormalBaudCalculator(Ifx_MSC *msc, uint32 baud)
138 {
139  float32 fsys = IfxScuCcu_getSpbFrequency();
140  uint32 step = 0;
141  uint32 df = 1;
142 
143  /* FDR.STEP = 1024 - fsys / DF*BR */
144 
145  if (msc->USR.B.URR != 0)
146  {
147  df = 1 << (msc->USR.B.URR + 1);
148  }
149  else
150  {
151  df = 0;
152  }
153 
154  step = 1024 - (fsys / (df * baud));
155 
156  return step;
157 }