iLLD_TC26xB
1.0
iLLD_TC26xB
IFX Low Level Drivers
Modules
Data Structures
Files
File List
Assert.c
Assert.h
Bsp.c
Bsp.h
CompilerDcc.c
CompilerDcc.h
CompilerGnuc.c
CompilerGnuc.h
Compilers.h
CompilerTasking.c
CompilerTasking.h
Icu.h
Ifx_Assert.h
Ifx_CircularBuffer.asm.c
Ifx_CircularBuffer.c
Ifx_CircularBuffer.h
Ifx_Console.c
Ifx_Console.h
Ifx_DateTime.c
Ifx_DateTime.h
Ifx_Fifo.c
Ifx_Fifo.h
Ifx_GlobalResources.c
Ifx_GlobalResources.h
Ifx_InternalMux.c
Ifx_InternalMux.h
Ifx_LowPassPt1.c
Ifx_LowPassPt1.h
Ifx_Shell.c
Ifx_Shell.h
Ifx_Types.h
Ifx_TypesDcc.h
Ifx_TypesGnuc.h
Ifx_TypesTasking.h
IfxAsclin.c
IfxAsclin.h
IfxAsclin_Asc.c
IfxAsclin_Asc.h
IfxAsclin_cfg.h
IfxAsclin_Lin.c
IfxAsclin_Lin.h
IfxAsclin_PinMap.c
IfxAsclin_PinMap.h
IfxAsclin_Spi.c
IfxAsclin_Spi.h
IfxCcu6.c
IfxCcu6.h
IfxCcu6_cfg.c
IfxCcu6_cfg.h
IfxCcu6_Icu.c
IfxCcu6_Icu.h
IfxCcu6_PinMap.c
IfxCcu6_PinMap.h
IfxCcu6_PwmBc.c
IfxCcu6_PwmBc.h
IfxCcu6_PwmHl.c
IfxCcu6_PwmHl.h
IfxCcu6_Timer.c
IfxCcu6_Timer.h
IfxCcu6_TimerWithTrigger.c
IfxCcu6_TimerWithTrigger.h
IfxCcu6_TPwm.c
IfxCcu6_TPwm.h
IfxCif.c
IfxCif.h
IfxCif_Cam.c
IfxCif_Cam.h
IfxCif_cfg.c
IfxCif_cfg.h
IfxCif_PinMap.c
IfxCif_PinMap.h
IfxCpu.c
IfxCpu.h
IfxCpu_cfg.c
IfxCpu_cfg.h
IfxCpu_CStart.h
IfxCpu_CStart0.c
IfxCpu_CStart1.c
IfxCpu_Intrinsics.h
IfxCpu_IntrinsicsDcc.h
IfxCpu_IntrinsicsGnuc.h
IfxCpu_IntrinsicsTasking.h
IfxCpu_Irq.c
IfxCpu_Irq.h
IfxCpu_Trap.c
IfxCpu_Trap.h
IfxDma.c
IfxDma.h
IfxDma_cfg.c
IfxDma_cfg.h
IfxDma_Dma.c
IfxDma_Dma.h
IfxDsadc.c
IfxDsadc.h
IfxDsadc_cfg.h
IfxDsadc_Dsadc.c
IfxDsadc_Dsadc.h
IfxDsadc_PinMap.c
IfxDsadc_PinMap.h
IfxDts.c
IfxDts.h
IfxDts_cfg.h
IfxDts_Dts.c
IfxDts_Dts.h
IfxEmem.c
IfxEmem.h
IfxEmem_cfg.h
IfxEray.c
IfxEray.h
IfxEray_cfg.h
IfxEray_Eray.c
IfxEray_Eray.h
IfxEray_PinMap.c
IfxEray_PinMap.h
IfxEth.c
IfxEth.h
IfxEth_cfg.h
IfxEth_Phy_Pef7071.c
IfxEth_Phy_Pef7071.h
IfxEth_PinMap.c
IfxEth_PinMap.h
IfxFce.c
IfxFce.h
IfxFce_cfg.h
IfxFce_Crc.c
IfxFce_Crc.h
IfxFft.c
IfxFft.h
IfxFft_cfg.h
IfxFft_Fft.c
IfxFft_Fft.h
IfxFlash.c
IfxFlash.h
IfxFlash_cfg.c
IfxFlash_cfg.h
IfxGlobal_cfg.h
IfxGpt12.c
IfxGpt12.h
IfxGpt12_cfg.h
IfxGpt12_IncrEnc.c
IfxGpt12_IncrEnc.h
IfxGpt12_PinMap.c
IfxGpt12_PinMap.h
IfxGtm.c
IfxGtm.h
IfxGtm_Atom.c
IfxGtm_Atom.h
IfxGtm_Atom_Pwm.c
IfxGtm_Atom_Pwm.h
IfxGtm_Atom_PwmHl.c
IfxGtm_Atom_PwmHl.h
IfxGtm_Atom_Timer.c
IfxGtm_Atom_Timer.h
IfxGtm_cfg.h
IfxGtm_Cmu.c
IfxGtm_Cmu.h
IfxGtm_Dpll.c
IfxGtm_Dpll.h
IfxGtm_PinMap.c
IfxGtm_PinMap.h
IfxGtm_Tbu.c
IfxGtm_Tbu.h
IfxGtm_Tim.c
IfxGtm_Tim.h
IfxGtm_Tom.c
IfxGtm_Tom.h
IfxGtm_Tom_Pwm.c
IfxGtm_Tom_Pwm.h
IfxGtm_Tom_PwmHl.c
IfxGtm_Tom_PwmHl.h
IfxGtm_Tom_Timer.c
IfxGtm_Tom_Timer.h
IfxGtm_Trig.c
IfxGtm_Trig.h
IfxHssl.c
IfxHssl.h
IfxHssl_cfg.h
IfxHssl_Hssl.c
IfxHssl_Hssl.h
IfxI2c.c
IfxI2c.h
IfxI2c_cfg.h
IfxI2c_I2c.c
IfxI2c_I2c.h
IfxI2c_PinMap.c
IfxI2c_PinMap.h
IfxIom.c
IfxIom.h
IfxIom_cfg.h
IfxIom_Iom.c
IfxIom_Iom.h
IfxLldVersion.h
IfxMsc.c
IfxMsc.h
IfxMsc_cfg.c
IfxMsc_cfg.h
IfxMsc_Msc.c
IfxMsc_Msc.h
IfxMsc_PinMap.c
IfxMsc_PinMap.h
IfxMtu.c
IfxMtu.h
IfxMtu_cfg.c
IfxMtu_cfg.h
IfxMultican.c
IfxMultican.h
IfxMultican_Can.c
IfxMultican_Can.h
IfxMultican_cfg.c
IfxMultican_cfg.h
IfxMultican_PinMap.c
IfxMultican_PinMap.h
IfxPort.c
IfxPort.h
IfxPort_cfg.c
IfxPort_cfg.h
IfxPort_Io.c
IfxPort_Io.h
IfxPort_PinMap.c
IfxPort_PinMap.h
IfxPsi5.c
IfxPsi5.h
IfxPsi5_cfg.c
IfxPsi5_cfg.h
IfxPsi5_PinMap.c
IfxPsi5_PinMap.h
IfxPsi5_Psi5.c
IfxPsi5_Psi5.h
IfxPsi5s.c
IfxPsi5s.h
IfxPsi5s_cfg.h
IfxPsi5s_PinMap.c
IfxPsi5s_PinMap.h
IfxPsi5s_Psi5s.c
IfxPsi5s_Psi5s.h
IfxQspi.c
IfxQspi.h
IfxQspi_cfg.h
IfxQspi_PinMap.c
IfxQspi_PinMap.h
IfxQspi_SpiMaster.c
IfxQspi_SpiMaster.h
IfxQspi_SpiSlave.c
IfxQspi_SpiSlave.h
IfxScu_cfg.c
IfxScu_cfg.h
IfxScu_PinMap.c
IfxScu_PinMap.h
IfxScuCcu.c
IfxScuCcu.h
IfxScuEru.c
IfxScuEru.h
IfxScuWdt.asm.h
IfxScuWdt.c
IfxScuWdt.h
IfxSent.c
IfxSent.h
IfxSent_cfg.c
IfxSent_cfg.h
IfxSent_PinMap.c
IfxSent_PinMap.h
IfxSent_Sent.c
IfxSent_Sent.h
IfxSmu_PinMap.c
IfxSmu_PinMap.h
IfxSrc.c
IfxSrc.h
IfxSrc_cfg.c
IfxSrc_cfg.h
IfxStdIf.h
IfxStdIf_DPipe.c
IfxStdIf_DPipe.h
IfxStdIf_Pos.c
IfxStdIf_Pos.h
IfxStdIf_PwmHl.c
IfxStdIf_PwmHl.h
IfxStdIf_Timer.c
IfxStdIf_Timer.h
IfxStm.c
IfxStm.h
IfxStm_cfg.c
IfxStm_cfg.h
IfxVadc.c
IfxVadc.h
IfxVadc_Adc.c
IfxVadc_Adc.h
IfxVadc_cfg.c
IfxVadc_cfg.h
IfxVadc_PinMap.c
IfxVadc_PinMap.h
lld_api.c
lld_codingRules.c
lld_codingRules_codeFormating.c
lld_codingRules_commonApis.c
lld_codingRules_if.c
lld_conventions.c
lld_conventionsDoxygen.c
lld_dosanddont.c
lld_dosanddont_enumUsage.c
lld_dosanddont_namingConvention.c
lld_dosanddont_optimisation.c
lld_filesAndConfig.c
lld_structure.c
lld_versioning.c
mainpage.c
Platform_Types.h
PwmHl.h
SpiIf.c
SpiIf.h
Timer.h
TPwm.h
Globals
IfxPsi5s.h
Go to the documentation of this file.
1
/**
2
* \file IfxPsi5s.h
3
* \brief PSI5S basic functionality
4
* \ingroup IfxLld_Psi5s
5
*
6
* \version iLLD_1_0_0_11_0
7
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8
*
9
*
10
* IMPORTANT NOTICE
11
*
12
*
13
* Infineon Technologies AG (Infineon) is supplying this file for use
14
* exclusively with Infineon's microcontroller products. This file can be freely
15
* distributed within development tools that are supporting such microcontroller
16
* products.
17
*
18
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23
*
24
* \defgroup IfxLld_Psi5s_Std_Enumerations Enumerations
25
* \ingroup IfxLld_Psi5s_Std
26
* \defgroup IfxLld_Psi5s_Std_Channel Channel Operative Functions
27
* \ingroup IfxLld_Psi5s_Std
28
* \defgroup IfxLld_Psi5s_Std_IO IO Pin Configuration Functions
29
* \ingroup IfxLld_Psi5s_Std
30
* \defgroup IfxLld_Psi5s_Std_Interrupt Interrupt configuration functions
31
* \ingroup IfxLld_Psi5s_Std
32
* \defgroup IfxLld_Psi5s_Std_Module Module Functions
33
* \ingroup IfxLld_Psi5s_Std
34
*/
35
36
#ifndef IFXPSI5S_H
37
#define IFXPSI5S_H 1
38
39
/******************************************************************************/
40
/*----------------------------------Includes----------------------------------*/
41
/******************************************************************************/
42
43
#include "
_Impl/IfxPsi5s_cfg.h
"
44
#include "
_PinMap/IfxPsi5s_PinMap.h
"
45
#include "
Cpu/Std/IfxCpu_Intrinsics.h
"
46
#include "IfxPsi5s_bf.h"
47
#include "IfxPsi5s_reg.h"
48
#include "
Src/Std/IfxSrc.h
"
49
#include "
Scu/Std/IfxScuCcu.h
"
50
51
/******************************************************************************/
52
/*--------------------------------Enumerations--------------------------------*/
53
/******************************************************************************/
54
55
/** \addtogroup IfxLld_Psi5s_Std_Enumerations
56
* \{ */
57
/** \brief MODULE_PSI5S.IOCR.ALTI:Alternate input
58
*/
59
typedef
enum
60
{
61
IfxPsi5s_AlternateInput_0
= 0,
/**< \brief Alternate Input 0 */
62
IfxPsi5s_AlternateInput_1
,
/**< \brief Alternate Input 1 */
63
IfxPsi5s_AlternateInput_2
,
/**< \brief Alternate Input 2 */
64
IfxPsi5s_AlternateInput_3
/**< \brief Alternate Input 3 */
65
}
IfxPsi5s_AlternateInput
;
66
67
/** \brief MODULE_PSI5S.BG.BR_VALUE:Baudrate prescalar select
68
*/
69
typedef
enum
70
{
71
IfxPsi5s_AscBaudratePrescalar_divideBy2
= 0,
/**< \brief Divide by 2 is selected for baudrate timer prescalar */
72
IfxPsi5s_AscBaudratePrescalar_divideBy3
= 1
/**< \brief Divide by 3 is selected for baudrate timer prescalar */
73
}
IfxPsi5s_AscBaudratePrescalar
;
74
75
/** \brief MODULE_PSI5S.CON.M:ASC mode of operation
76
*/
77
typedef
enum
78
{
79
IfxPsi5s_AscMode_sync
= 0,
/**< \brief Synchronous mode */
80
IfxPsi5s_AscMode_async_8bitData
= 1,
/**< \brief Asynchronous mode with 8 bit data */
81
IfxPsi5s_AscMode_async_7bitDataWithParity
= 3,
/**< \brief Asynchronous mode with 7 bit data with parity */
82
IfxPsi5s_AscMode_async_9bitData
= 4,
/**< \brief Asynchronous mode with 9 bit data */
83
IfxPsi5s_AscMode_async_8bitDataWithWakeup
= 5,
/**< \brief Asynchronous mode with 8 bit data with wakeup */
84
IfxPsi5s_AscMode_async_8bitDataWithParity
= 7
/**< \brief Asynchronous mode with 8 bit data with parity */
85
}
IfxPsi5s_AscMode
;
86
87
/** \brief MODULE_PSI5S.CON.STP: Number of stop bits
88
*/
89
typedef
enum
90
{
91
IfxPsi5s_AscStopBits_1
= 0,
/**< \brief 1 stop bit */
92
IfxPsi5s_AscStopBits_2
/**< \brief 2 stop bit */
93
}
IfxPsi5s_AscStopBits
;
94
95
/** \brief PSI5S Channel Id defined in MODULE_PSI5S.RDS.B.CID.
96
*/
97
typedef
enum
98
{
99
IfxPsi5s_ChannelId_0
= 0,
/**< \brief Ifx_PSI5S Channel 0 */
100
IfxPsi5s_ChannelId_1
,
/**< \brief Ifx_PSI5S Channel 1 */
101
IfxPsi5s_ChannelId_2
,
/**< \brief Ifx_PSI5S Channel 2 */
102
IfxPsi5s_ChannelId_3
,
/**< \brief Ifx_PSI5S Channel 3 */
103
IfxPsi5s_ChannelId_4
,
/**< \brief Ifx_PSI5S Channel 4 */
104
IfxPsi5s_ChannelId_5
,
/**< \brief Ifx_PSI5S Channel 5 */
105
IfxPsi5s_ChannelId_6
,
/**< \brief Ifx_PSI5S Channel 6 */
106
IfxPsi5s_ChannelId_7
,
/**< \brief Ifx_PSI5S Channel 7 */
107
IfxPsi5s_ChannelId_none
= -1
/**< \brief None of the Ifx_PSI5S Channels */
108
}
IfxPsi5s_ChannelId
;
109
110
/** \brief Clock Selection
111
*/
112
typedef
enum
113
{
114
IfxPsi5s_ClockType_fracDiv
= 0,
/**< \brief Fractional Divide clock */
115
IfxPsi5s_ClockType_timeStamp
= 1,
/**< \brief Timestamp clock */
116
IfxPsi5s_ClockType_ascFracDiv
= 2,
/**< \brief Asc Fractional divider clock */
117
IfxPsi5s_ClockType_ascOutput
= 3
/**< \brief Asc output clock */
118
}
IfxPsi5s_ClockType
;
119
120
/** \brief MODULE_PSI5S.RCRAx.CRCy(x= 0,1,..7:y=0,1,..,5),MODULE_PSI5S.RCRBx.CRCy(x= 0,1,..7:y=0,1,..,5)CRC or parity
121
*/
122
typedef
enum
123
{
124
IfxPsi5s_CrcOrParity_parity
= 0,
/**< \brief parity selection */
125
IfxPsi5s_CrcOrParity_crc
= 1
/**< \brief CRC selection */
126
}
IfxPsi5s_CrcOrParity
;
127
128
/** \brief MODULE_PSI5S.FDR.DM;MODULE_PSI5S.FDRT.B.DM:Divider mode
129
*/
130
typedef
enum
131
{
132
IfxPsi5s_DividerMode_spb
= 0,
/**< \brief divider mode is off */
133
IfxPsi5s_DividerMode_normal
= 1,
/**< \brief divider mode is normal */
134
IfxPsi5s_DividerMode_fractional
= 2,
/**< \brief divider mode is fractional */
135
IfxPsi5s_DividerMode_off
= 3
/**< \brief divider mode is off */
136
}
IfxPsi5s_DividerMode
;
137
138
/** \brief MODULE_PSI5S.SCRx.EPS(x=0,1,...,7):Enhanced protocol types
139
*/
140
typedef
enum
141
{
142
IfxPsi5s_EnhancedProtocol_toothGapMethod
= 0,
/**< \brief toothGapMethod Enhanced protocol type */
143
IfxPsi5s_EnhancedProtocol_pulseWidth_frameFormat_1to3
= 1,
/**< \brief pulseWidth_frameFormat_1to3 Enhanced protocol type */
144
IfxPsi5s_EnhancedProtocol_pulseWidth_frameFormat_4
= 3
/**< \brief pulseWidth_frameFormat_4 Enhanced protocol type */
145
}
IfxPsi5s_EnhancedProtocol
;
146
147
/** \brief MODULE_PSI5S.RCRAx.FIDS(x=0,1,....,7):.Frame ID updation
148
*/
149
typedef
enum
150
{
151
IfxPsi5s_FrameId_frameHeader
= 0,
/**< \brief Frame ID is updated from packet frame header (Sync mode) */
152
IfxPsi5s_FrameId_rollingNumber
= 1
/**< \brief Frame ID is a rolling number 0 .. 5 copied from FCNT */
153
}
IfxPsi5s_FrameId
;
154
155
/** \brief MODULE_PSI5S.GCR.IDT:Idle time bit count
156
*/
157
typedef
enum
158
{
159
IfxPsi5s_IdleTime_1
= 0,
/**< \brief 1 bit Idle time */
160
IfxPsi5s_IdleTime_2
,
/**< \brief 2 bit Idle time */
161
IfxPsi5s_IdleTime_3
,
/**< \brief 3 bit Idle time */
162
IfxPsi5s_IdleTime_4
,
/**< \brief 4 bit Idle time */
163
IfxPsi5s_IdleTime_5
,
/**< \brief 5 bit Idle time */
164
IfxPsi5s_IdleTime_6
,
/**< \brief 6 bit Idle time */
165
IfxPsi5s_IdleTime_7
,
/**< \brief 7 bit Idle time */
166
IfxPsi5s_IdleTime_8
,
/**< \brief 8 bit Idle time */
167
IfxPsi5s_IdleTime_9
,
/**< \brief 9 bit Idle time */
168
IfxPsi5s_IdleTime_10
,
/**< \brief 10 bit Idle time */
169
IfxPsi5s_IdleTime_11
,
/**< \brief 11 bit Idle time */
170
IfxPsi5s_IdleTime_12
,
/**< \brief 12 bit Idle time */
171
IfxPsi5s_IdleTime_13
,
/**< \brief 13 bit Idle time */
172
IfxPsi5s_IdleTime_14
,
/**< \brief 14 bit Idle time */
173
IfxPsi5s_IdleTime_15
,
/**< \brief 15 bit Idle time */
174
IfxPsi5s_IdleTime_16
/**< \brief 16 bit Idle time */
175
}
IfxPsi5s_IdleTime
;
176
177
/** \brief Messaging bits presence
178
*/
179
typedef
enum
180
{
181
IfxPsi5s_MessagingBits_absent
= 0,
/**< \brief No messaging bits */
182
IfxPsi5s_MessagingBits_present
= 1
/**< \brief 2 messaging bits */
183
}
IfxPsi5s_MessagingBits
;
184
185
/** \brief MODULE_PSI5S.NFC.NFx:Expected Psi5s frames
186
*/
187
typedef
enum
188
{
189
IfxPsi5s_NumberExpectedFrames_1
= 1,
/**< \brief 1 psi5s frame expected */
190
IfxPsi5s_NumberExpectedFrames_2
,
/**< \brief 2 psi5s frame expected */
191
IfxPsi5s_NumberExpectedFrames_3
,
/**< \brief 3 psi5s frame expected */
192
IfxPsi5s_NumberExpectedFrames_4
,
/**< \brief 4 psi5s frame expected */
193
IfxPsi5s_NumberExpectedFrames_5
,
/**< \brief 5 psi5s frame expected */
194
IfxPsi5s_NumberExpectedFrames_6
/**< \brief 6 psi5s frame expected */
195
}
IfxPsi5s_NumberExpectedFrames
;
196
197
/** \brief Enable/disable the sensitivity of the module to sleep signal\n
198
* Definition in Ifx_PSI5S.CLC.B.EDIS
199
*/
200
typedef
enum
201
{
202
IfxPsi5s_SleepMode_enable
= 0,
/**< \brief enables sleep mode */
203
IfxPsi5s_SleepMode_disable
= 1
/**< \brief disables sleep mode */
204
}
IfxPsi5s_SleepMode
;
205
206
/** \brief MODULE_PSI5S.TSCNTA.B.TBS;MODULE_PSI5S.TSCNTB.B.TBS:Time base
207
*/
208
typedef
enum
209
{
210
IfxPsi5s_TimeBase_internal
= 0,
/**< \brief Internal time stamp clock */
211
IfxPsi5s_TimeBase_external
= 1
/**< \brief External GTM inputs */
212
}
IfxPsi5s_TimeBase
;
213
214
/** \brief MODULE_PSI5S.TSCNTx(x= A,B):Timestamp register
215
*/
216
typedef
enum
217
{
218
IfxPsi5s_TimestampRegister_a
= 0,
/**< \brief Timestamp register A */
219
IfxPsi5s_TimestampRegister_b
= 1
/**< \brief Timestamp register B */
220
}
IfxPsi5s_TimestampRegister
;
221
222
/** \brief MODULE_PSI5S.RCRAx.TSTS:Timestamp trigger
223
*/
224
typedef
enum
225
{
226
IfxPsi5s_TimestampTrigger_syncPulse
= 0,
/**< \brief Timestamp trigger on sync pulse */
227
IfxPsi5s_TimestampTrigger_frame
= 1
/**< \brief Timestamp trigger on any frame */
228
}
IfxPsi5s_TimestampTrigger
;
229
230
/** \brief MODULE_PSI5S.TSCNTA.B.ETB;MODULE_PSI5S.TSCNTB.B.ETB:Trigger Id
231
*/
232
typedef
enum
233
{
234
IfxPsi5s_Trigger_0
= 0,
/**< \brief Trigger 0 */
235
IfxPsi5s_Trigger_1
,
/**< \brief Trigger 1 */
236
IfxPsi5s_Trigger_2
,
/**< \brief Trigger 2 */
237
IfxPsi5s_Trigger_3
,
/**< \brief Trigger 3 */
238
IfxPsi5s_Trigger_4
,
/**< \brief Trigger 4 */
239
IfxPsi5s_Trigger_5
,
/**< \brief Trigger 5 */
240
IfxPsi5s_Trigger_6
,
/**< \brief Trigger 6 */
241
IfxPsi5s_Trigger_7
/**< \brief Trigger 7 */
242
}
IfxPsi5s_Trigger
;
243
244
/** \brief Trigger type defined in
245
*/
246
typedef
enum
247
{
248
IfxPsi5s_TriggerType_periodic
= 0,
/**< \brief Periodic trigger */
249
IfxPsi5s_TriggerType_external
= 1
/**< \brief External trigger */
250
}
IfxPsi5s_TriggerType
;
251
252
/** \brief MODULE_PSI5S.RCRAx.UFCY(x=0,1,...7;y=0,1...5):UART frame count
253
*/
254
typedef
enum
255
{
256
IfxPsi5s_UartFrameCount_3
= 0,
/**< \brief 3 UART frames */
257
IfxPsi5s_UartFrameCount_4
,
/**< \brief 4 UART frames */
258
IfxPsi5s_UartFrameCount_5
,
/**< \brief 5 UART frames */
259
IfxPsi5s_UartFrameCount_6
/**< \brief 6 UART frames */
260
}
IfxPsi5s_UartFrameCount
;
261
262
/** \brief MODULE_PSI5S.RCRAx.WDMS:Watchdog timer mode
263
*/
264
typedef
enum
265
{
266
IfxPsi5s_WatchdogTimerMode_frame
= 0,
/**< \brief Watch Dog Timer is restarted on reception of each recoverable frame (async mode) */
267
IfxPsi5s_WatchdogTimerMode_syncPulse
= 1
/**< \brief Watch Dog Timer is restarted on Sync Pulse and stopped at reception of the last frame configured in NFC.NFx.(sync mode) */
268
}
IfxPsi5s_WatchdogTimerMode
;
269
270
/** \} */
271
272
/** \addtogroup IfxLld_Psi5s_Std_Channel
273
* \{ */
274
275
/******************************************************************************/
276
/*-------------------------Global Function Prototypes-------------------------*/
277
/******************************************************************************/
278
279
/** \brief Enable ASC receiver
280
* \param psi5s pointer to the PSI5S register space
281
* \return None
282
*/
283
IFX_EXTERN
void
IfxPsi5s_enableAscReceiver
(Ifx_PSI5S *psi5s);
284
285
/** \brief Enable/disable any combination of channel trigger counters selected by mask parameter
286
* \param psi5s pointer to the PSI5S register space
287
* \param channels specifies the channel trigger counters which should be enabled/disabled
288
* \param mask specifies the channel trigger counters which should be modified
289
* \return None
290
*/
291
IFX_EXTERN
void
IfxPsi5s_enableDisableChannelTriggerCounters
(Ifx_PSI5S *psi5s,
uint32
channels,
uint32
mask);
292
293
/** \brief Enable/disable any combination of channels selected by mask parameter
294
* \param psi5s pointer to the PSI5S register space
295
* \param channels specifies the channels which should be enabled/disabled
296
* \param mask specifies the channels which should be modified
297
* \return None
298
*/
299
IFX_EXTERN
void
IfxPsi5s_enableDisableChannels
(Ifx_PSI5S *psi5s,
uint32
channels,
uint32
mask);
300
301
/** \brief Start ASC transactions
302
* \param psi5s pointer to the PSI5S register space
303
* \return None
304
*/
305
IFX_EXTERN
void
IfxPsi5s_startAscTransactions
(Ifx_PSI5S *psi5s);
306
307
/** \} */
308
309
/** \addtogroup IfxLld_Psi5s_Std_IO
310
* \{ */
311
312
/******************************************************************************/
313
/*-------------------------Inline Function Prototypes-------------------------*/
314
/******************************************************************************/
315
316
/** \brief Initializes a CLK output
317
* \param clk the CLK Pin which should be configured
318
* \param outputMode the pin output mode which should be configured
319
* \param padDriver the pad driver mode which should be configured
320
* \return None
321
*/
322
IFX_INLINE
void
IfxPsi5s_initClkPin
(
const
IfxPsi5s_Clk_Out
*clk,
IfxPort_OutputMode
outputMode,
IfxPort_PadDriver
padDriver);
323
324
/** \brief Initializes a RX input
325
* \param rx the RX Pin which should be configured
326
* \param inputMode the pin input mode which should be configured
327
* \return None
328
*/
329
IFX_INLINE
void
IfxPsi5s_initRxPin
(
const
IfxPsi5s_Rx_In
*rx,
IfxPort_InputMode
inputMode);
330
331
/** \brief Initializes a TX output
332
* \param tx the TX Pin which should be configured
333
* \param outputMode the pin output mode which should be configured
334
* \param padDriver the pad driver mode which should be configured
335
* \return None
336
*/
337
IFX_INLINE
void
IfxPsi5s_initTxPin
(
const
IfxPsi5s_Tx_Out
*tx,
IfxPort_OutputMode
outputMode,
IfxPort_PadDriver
padDriver);
338
339
/** \brief Selects the alternate input for Rx signal
340
* \param psi5s pointer to PSI5S registers
341
* \param alti alternate input selection of Rx signal
342
* \return None
343
*/
344
IFX_INLINE
void
IfxPsi5s_setRxInput
(Ifx_PSI5S *psi5s,
IfxPsi5s_AlternateInput
alti);
345
346
/** \} */
347
348
/** \addtogroup IfxLld_Psi5s_Std_Module
349
* \{ */
350
351
/******************************************************************************/
352
/*-------------------------Inline Function Prototypes-------------------------*/
353
/******************************************************************************/
354
355
/** \brief enable / disable sleep mode
356
* \param psi5s Pointer to PSI5S register
357
* \param mode sleep mode (enable/disable)
358
* \return None
359
*/
360
IFX_INLINE
void
IfxPsi5s_setSleepMode
(Ifx_PSI5S *psi5s,
IfxPsi5s_SleepMode
mode);
361
362
/******************************************************************************/
363
/*-------------------------Global Function Prototypes-------------------------*/
364
/******************************************************************************/
365
366
/** \brief resets PSI5S kernel
367
* \param psi5s pointer to PSI5S registers
368
* \return None
369
*/
370
IFX_EXTERN
void
IfxPsi5s_resetModule
(Ifx_PSI5S *psi5s);
371
372
/** \} */
373
374
/******************************************************************************/
375
/*-------------------------Global Function Prototypes-------------------------*/
376
/******************************************************************************/
377
378
/** \brief Get the received psi5s frame for the channel
379
* \param psi5s Pointer to PSI5S Module
380
* \param channelId channel ID
381
* \return Frame Status
382
*/
383
IFX_EXTERN
boolean
IfxPsi5s_getReadFrameStatus
(Ifx_PSI5S *psi5s,
IfxPsi5s_ChannelId
channelId);
384
385
/******************************************************************************/
386
/*---------------------Inline Function Implementations------------------------*/
387
/******************************************************************************/
388
389
IFX_INLINE
void
IfxPsi5s_initClkPin
(
const
IfxPsi5s_Clk_Out
*clk,
IfxPort_OutputMode
outputMode,
IfxPort_PadDriver
padDriver)
390
{
391
IfxPort_setPinModeOutput
(clk->
pin
.
port
, clk->
pin
.
pinIndex
, outputMode, clk->
select
);
392
IfxPort_setPinPadDriver
(clk->
pin
.
port
, clk->
pin
.
pinIndex
, padDriver);
393
}
394
395
396
IFX_INLINE
void
IfxPsi5s_initRxPin
(
const
IfxPsi5s_Rx_In
*rx,
IfxPort_InputMode
inputMode)
397
{
398
IfxPort_setPinModeInput
(rx->
pin
.
port
, rx->
pin
.
pinIndex
, inputMode);
399
IfxPsi5s_setRxInput
(rx->
module
, (
IfxPsi5s_AlternateInput
)rx->
select
);
400
}
401
402
403
IFX_INLINE
void
IfxPsi5s_initTxPin
(
const
IfxPsi5s_Tx_Out
*tx,
IfxPort_OutputMode
outputMode,
IfxPort_PadDriver
padDriver)
404
{
405
IfxPort_setPinModeOutput
(tx->
pin
.
port
, tx->
pin
.
pinIndex
, outputMode, tx->
select
);
406
IfxPort_setPinPadDriver
(tx->
pin
.
port
, tx->
pin
.
pinIndex
, padDriver);
407
}
408
409
410
IFX_INLINE
void
IfxPsi5s_setRxInput
(Ifx_PSI5S *psi5s,
IfxPsi5s_AlternateInput
alti)
411
{
412
psi5s->IOCR.B.ALTI = alti;
413
}
414
415
416
IFX_INLINE
void
IfxPsi5s_setSleepMode
(Ifx_PSI5S *psi5s,
IfxPsi5s_SleepMode
mode)
417
{
418
uint16
passwd =
IfxScuWdt_getCpuWatchdogPassword
();
419
IfxScuWdt_clearCpuEndinit
(passwd);
420
psi5s->CLC.B.EDIS = mode;
421
IfxScuWdt_setCpuEndinit
(passwd);
422
}
423
424
425
#endif
/* IFXPSI5S_H */
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src
ifx
TC26xB
Psi5s
Std
IfxPsi5s.h
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