iLLD_TC23x  1.0
IfxDma.h
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1 /**
2  * \file IfxDma.h
3  * \brief DMA basic functionality
4  * \ingroup IfxLld_Dma
5  *
6  * \version iLLD_1_0_0_11_0
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Dma_Std_Enum Enumerations
25  * \ingroup IfxLld_Dma_Std
26  * \defgroup IfxLld_Dma_Std_Reset Reset Functions
27  * \ingroup IfxLld_Dma_Std
28  * \defgroup IfxLld_Dma_Std_Channel_Transaction Channel Transaction Functions
29  * \ingroup IfxLld_Dma_Std
30  * \defgroup IfxLld_Dma_Std_Move_Engine Move Engine functions
31  * \ingroup IfxLld_Dma_Std
32  * \defgroup IfxLld_Dma_Std_Channel_Configure Channel configuration Functions
33  * \ingroup IfxLld_Dma_Std
34  * \defgroup IfxLld_Dma_Std_Channel_Halt Channel Halt Functions
35  * \ingroup IfxLld_Dma_Std
36  * \defgroup IfxLld_Dma_Std_Double_Buffer Double Buffer functions
37  * \ingroup IfxLld_Dma_Std
38  * \defgroup IfxLld_Dma_Std_Interrupts Interrupt functions
39  * \ingroup IfxLld_Dma_Std
40  */
41 
42 #ifndef IFXDMA_H
43 #define IFXDMA_H 1
44 
45 /******************************************************************************/
46 /*----------------------------------Includes----------------------------------*/
47 /******************************************************************************/
48 
49 #include "_Impl/IfxDma_cfg.h"
50 #include "IfxDma_bf.h"
52 #include "IfxDma_reg.h"
53 #include "Src/Std/IfxSrc.h"
54 #include "Scu/Std/IfxScuWdt.h"
55 #include "Scu/Std/IfxScuCcu.h"
56 
57 /******************************************************************************/
58 /*--------------------------------Enumerations--------------------------------*/
59 /******************************************************************************/
60 
61 /** \addtogroup IfxLld_Dma_Std_Enum
62  * \{ */
63 /** \brief Bus Master Mode definition
64  * Definition in Ifx_DMA.MODE[4].B.MODE
65  */
66 typedef enum
67 {
68  IfxDma_BusMasterMode_user = 0, /**< \brief Selected hardware resource performs Bus access in user mode */
69  IfxDma_BusMasterMode_supervisor = 1 /**< \brief Selected hardware resource performs Bus access in supervisor mode */
71 
72 /** \brief Channel Bus Priority definition
73  */
74 typedef enum
75 {
76  IfxDma_ChannelBusPriority_low = 0, /**< \brief low priority */
77  IfxDma_ChannelBusPriority_medium = 1, /**< \brief medium priority */
78  IfxDma_ChannelBusPriority_high = 2 /**< \brief high priority */
80 
81 /** \brief DMA circular buffer (wrap around) definition
82  * Definition in Ifx_DMA.CH[64].ADICR.B.CBLS and Ifx_DMA.CH[64].ADICR.B.CBLD
83  */
84 typedef enum
85 {
86  IfxDma_ChannelIncrementCircular_none = 0, /**< \brief no circular buffer operation */
87  IfxDma_ChannelIncrementCircular_2 = 1, /**< \brief circular buffer size is 2 byte */
88  IfxDma_ChannelIncrementCircular_4 = 2, /**< \brief circular buffer size is 4 byte */
89  IfxDma_ChannelIncrementCircular_8 = 3, /**< \brief circular buffer size is 8 byte */
90  IfxDma_ChannelIncrementCircular_16 = 4, /**< \brief circular buffer size is 16 byte */
91  IfxDma_ChannelIncrementCircular_32 = 5, /**< \brief circular buffer size is 32 byte */
92  IfxDma_ChannelIncrementCircular_64 = 6, /**< \brief circular buffer size is 64 byte */
93  IfxDma_ChannelIncrementCircular_128 = 7, /**< \brief circular buffer size is 128 byte */
94  IfxDma_ChannelIncrementCircular_256 = 8, /**< \brief circular buffer size is 256 byte */
95  IfxDma_ChannelIncrementCircular_512 = 9, /**< \brief circular buffer size is 512 byte */
96  IfxDma_ChannelIncrementCircular_1024 = 10, /**< \brief circular buffer size is 1024 byte */
97  IfxDma_ChannelIncrementCircular_2048 = 11, /**< \brief circular buffer size is 2048 byte */
98  IfxDma_ChannelIncrementCircular_4096 = 12, /**< \brief circular buffer size is 4096 byte */
99  IfxDma_ChannelIncrementCircular_8192 = 13, /**< \brief circular buffer size is 8192 byte */
100  IfxDma_ChannelIncrementCircular_16384 = 14, /**< \brief circular buffer size is 16384 byte */
101  IfxDma_ChannelIncrementCircular_32768 = 15 /**< \brief circular buffer size is 32768 byte */
103 
104 /** \brief DMA incrementation direction definition
105  * Definition in Ifx_DMA.CH[64].ADICR.B.INCS
106  */
107 typedef enum
108 {
109  IfxDma_ChannelIncrementDirection_negative = 0, /**< \brief pointer is decremented */
110  IfxDma_ChannelIncrementDirection_positive = 1 /**< \brief pointer is incremented */
112 
113 /** \brief DMA incrementation definition
114  * Definition in Ifx_DMA.CH[64].ADICR.B.SMF
115  */
116 typedef enum
117 {
118  IfxDma_ChannelIncrementStep_1 = 0, /**< \brief increment by 1 width */
119  IfxDma_ChannelIncrementStep_2 = 1, /**< \brief increment by 2 width */
120  IfxDma_ChannelIncrementStep_4 = 2, /**< \brief increment by 4 width */
121  IfxDma_ChannelIncrementStep_8 = 3, /**< \brief increment by 8 width */
122  IfxDma_ChannelIncrementStep_16 = 4, /**< \brief increment by 16 width */
123  IfxDma_ChannelIncrementStep_32 = 5, /**< \brief increment by 32 width */
124  IfxDma_ChannelIncrementStep_64 = 6, /**< \brief increment by 64 width */
125  IfxDma_ChannelIncrementStep_128 = 7 /**< \brief increment by 128 width */
127 
128 /** \brief Channel Transfer Interrupt generation mechanism.
129  * Definition in Ifx_DMA.CH[64].ADICR.B.INTCT (bit 0)
130  */
131 typedef enum
132 {
133  IfxDma_ChannelInterruptControl_thresholdLimitMatch = 0, /**< \brief interrupt when transfer count (TCOUNT) equals the threshold limit (IRDV) */
134  IfxDma_ChannelInterruptControl_transferCountDecremented = 1 /**< \brief interrupt when transfer count (TCOUNT) is decremented */
136 
137 /** \brief DMA transfer definition
138  * Definition in Ifx_DMA.BLK0.ME.CHCR.B.BLKM and Ifx_DMA.BLK1.ME.CHCR.B.BLKM
139  */
140 typedef enum
141 {
142  IfxDma_ChannelMove_1 = 0, /**< \brief 1 DMA move per DMA transfer */
143  IfxDma_ChannelMove_2 = 1, /**< \brief 2 DMA move per DMA transfer */
144  IfxDma_ChannelMove_4 = 2, /**< \brief 4 DMA move per DMA transfer */
145  IfxDma_ChannelMove_8 = 3, /**< \brief 8 DMA move per DMA transfer */
146  IfxDma_ChannelMove_16 = 4, /**< \brief 16 DMA move per DMA transfer */
147  IfxDma_ChannelMove_3 = 5, /**< \brief 3 DMA move per DMA transfer */
148  IfxDma_ChannelMove_5 = 6, /**< \brief 5 DMA move per DMA transfer */
149  IfxDma_ChannelMove_9 = 7 /**< \brief 9 DMA move per DMA transfer */
151 
152 /** \brief DMA move size definition
153  * Definition in Ifx_DMA.BLK0.ME.CHCR.B.CHDW and Ifx_DMA.BLK1.ME.CHCR.B.CHDW
154  */
155 typedef enum
156 {
157  IfxDma_ChannelMoveSize_8bit = 0, /**< \brief 1 DMA move is 8 bit wide */
158  IfxDma_ChannelMoveSize_16bit = 1, /**< \brief 1 DMA move is 16 bit wide */
159  IfxDma_ChannelMoveSize_32bit = 2, /**< \brief 1 DMA move is 32 bit wide */
160  IfxDma_ChannelMoveSize_64bit = 3, /**< \brief 1 DMA move is 64 bit wide */
161  IfxDma_ChannelMoveSize_128bit = 4, /**< \brief 1 DMA move is 128 bit wide */
162  IfxDma_ChannelMoveSize_256bit = 5 /**< \brief 1 DMA move is 256 bit wide */
164 
165 /** \brief DMA operation mode
166  * Definition in Ifx_DMA.BLK0.ME.CHCR.B.CHMODE and Ifx_DMA.BLK1.ME.CHCR.B.CHMODE
167  */
168 typedef enum
169 {
170  IfxDma_ChannelOperationMode_single = 0, /**< \brief channel disabled after transaction */
171  IfxDma_ChannelOperationMode_continuous = 1 /**< \brief channel stays enabled after transaction */
173 
174 /** \brief Pattern detection selection
175  * Definition in Ifx_DMA.BLK0.ME.CHCR.B.PATSEL and Ifx_DMA.BLK1.ME.CHCR.B.PATSEL
176  */
177 typedef enum
178 {
179  IfxDma_ChannelPattern_0_disable = 0, /**< \brief Pattern detect 0 disabled */
180  IfxDma_ChannelPattern_0_mode1 = 1, /**< \brief Compare match configuration 1 : pattern compare of MExR.RD[0] to PAT0[0] masked by PAT0[2] */
181  IfxDma_ChannelPattern_0_mode2 = 2, /**< \brief Compare match configuration 2 : pattern compare of MExR.RD[0] to PAT0[1] masked by PAT0[3] */
182  IfxDma_ChannelPattern_0_mode3 = 3, /**< \brief Compare match configuration 3 : pattern compare of MExR.RD[0] to PAT0[0] masked by PAT0[2] of actual DMA read move and pattern compare of MExR.RD[0] to PAT0[1] masked by PAT0[3] of previous DMA read move */
183  IfxDma_ChannelPattern_1_disable = 4, /**< \brief Pattern detect 1 disabled */
184  IfxDma_ChannelPattern_1_mode1 = 5, /**< \brief Compare match configuration 1 : pattern compare of MExR.RD[0] to PAT1[0] masked by PAT1[2] */
185  IfxDma_ChannelPattern_1_mode2 = 6, /**< \brief Compare match configuration 2 : pattern compare of MExR.RD[0] to PAT1[1] masked by PAT1[3] */
186  IfxDma_ChannelPattern_1_mode3 = 7 /**< \brief Compare match configuration 3 : pattern compare of MExR.RD[0] to PAT1[0] masked by PAT1[2] of actual DMA read move and pattern compare of MExR.RD[0] to PAT1[1] masked by PAT1[3] of previous DMA read move */
188 
189 /** \brief Channel Priority definition
190  */
191 typedef enum
192 {
193  IfxDma_ChannelPriority_low = 0, /**< \brief low priority */
194  IfxDma_ChannelPriority_medium = 1, /**< \brief medium priority */
195  IfxDma_ChannelPriority_high = 2 /**< \brief high priority */
197 
198 /** \brief DMA request mode
199  * Definition in Ifx_DMA.BLK0.ME.CHCR.B.RROAT and Ifx_DMA.BLK1.ME.CHCR.B.RROAT
200  */
201 typedef enum
202 {
203  IfxDma_ChannelRequestMode_oneTransferPerRequest = 0, /**< \brief a request initiates a single transfer */
204  IfxDma_ChannelRequestMode_completeTransactionPerRequest = 1 /**< \brief a request initiates a complete transaction */
206 
207 /** \brief DMA request selection
208  * Definition in Ifx_DMA.BLK0.ME.CHCR.B.PRSEL and Ifx_DMA.BLK1.ME.CHCR.B.PRSEL
209  */
210 typedef enum
211 {
212  IfxDma_ChannelRequestSource_peripheral = 0, /**< \brief Transfer Request via Hardware Trigger */
213  IfxDma_ChannelRequestSource_daisyChain = 1 /**< \brief Transfer Request via next (higher priority) channel */
215 
216 /** \brief shadow definition definition
217  * Definition in Ifx_DMA.CH[64].ADICR.B.SHCT
218  */
219 typedef enum
220 {
221  IfxDma_ChannelShadow_none = 0, /**< \brief shadow address register not used. Source and destination address register are written directly */
222  IfxDma_ChannelShadow_src = 1, /**< \brief Shadow address register used for source address buffering. When writing to SADRmx, the address is buffered in SHADRmx and transferred to SADRmx with the start of the next DMA transaction */
223  IfxDma_ChannelShadow_dst = 2, /**< \brief Shadow address register used for destination address buffering. When writing to DADRmx, the address is buffered in SHADRmx and transferred to DADRmx with the start of the next DMA transaction */
224  IfxDma_ChannelShadow_srcDirectWrite = 5, /**< \brief Shadow address used for source buffering. When writing to SADRz, the address is buffered in SHADRz and transferred to SADRz with the start of the next DMA transaction */
225  IfxDma_ChannelShadow_dstDirectWrite = 6, /**< \brief Shadow address used for destination buffering. When writing to DADRz, the address is buffered in SHADRz and transferred to DADRz with the start of the next DMA transaction */
226  IfxDma_ChannelShadow_doubleSourceBufferingSwSwitch = 8, /**< \brief Software switch only. Shadow address used for double buffering */
227  IfxDma_ChannelShadow_doubleSourceBufferingHwSwSwitch = 9, /**< \brief Automatic Hardware and Software switch. Shadow address used for double buffering */
228  IfxDma_ChannelShadow_doubleDestinationBufferingSwSwitch = 10, /**< \brief Software switch only. Shadow address used for double buffering */
229  IfxDma_ChannelShadow_doubleDestinationBufferingHwSwSwitch = 11, /**< \brief Automatic Hardware and Software switch. Shadow address used for double buffering */
230  IfxDma_ChannelShadow_linkedList = 12, /**< \brief The DMA controller reads a DMA channel transaction control set and overwrites 8 X words in the corresponding DMARAM channel z */
231  IfxDma_ChannelShadow_accumulatedLinkedList = 13, /**< \brief The DMA controller reads a DMA channel transaction control set and overwrites 6 X words in the corresponding DMARAM channel z */
232  IfxDma_ChannelShadow_safeLinkedList = 14, /**< \brief The DMA controller reads a DMA channel transaction control set. The Linked List only proceeds with the next DMA transaction if the existing SDCRC checksum matches the expected SDCRC checksum in the loaded from the new DMA transaction control set */
233  IfxDma_ChannelShadow_conditionalLinkedList = 15 /**< \brief Shadow address register (MExSHADR) and source and destination address CRC register (MExSDCRC) are used as address pointers to a Linked List. The selection of the address pointer is determined by DMA channel pattern detection conditions */
235 
236 typedef enum
237 {
238  IfxDma_HardwareResourcePartition_0 = 0, /**< \brief "Set of DMA channels are associated with hardware resource partition " + str(x) */
239  IfxDma_HardwareResourcePartition_1, /**< \brief "Set of DMA channels are associated with hardware resource partition " + str(x) */
240  IfxDma_HardwareResourcePartition_2, /**< \brief "Set of DMA channels are associated with hardware resource partition " + str(x) */
241  IfxDma_HardwareResourcePartition_3 /**< \brief "Set of DMA channels are associated with hardware resource partition " + str(x) */
243 
244 /** \brief DMA move engine definition
245  */
246 typedef enum
247 {
248  IfxDma_MoveEngine_0 = 0 /**< \brief first move engine */
250 
251 /** \brief Enable/disable the sensitivity of the module to sleep signal\n
252  * Definition in Ifx_DMA.CLC.B.EDIS
253  */
254 typedef enum
255 {
256  IfxDma_SleepMode_enable = 0, /**< \brief enables sleep mode */
257  IfxDma_SleepMode_disable = 1 /**< \brief disables sleep mode */
259 
260 /** \} */
261 
262 /** \addtogroup IfxLld_Dma_Std_Reset
263  * \{ */
264 
265 /******************************************************************************/
266 /*-------------------------Inline Function Prototypes-------------------------*/
267 /******************************************************************************/
268 
269 /** \brief Return the status of a DMA channel (reset / not reset)
270  * \param dma pointer to DMA module
271  * \param channelId DMA channel number
272  * \return TRUE if the channel is reset
273  * FALSE if the channel is not reset
274  *
275  * \code
276  * // check whether the channel is reset or not and also the hardware trigger disabled
277  *
278  * if (IfxDma_isChannelReset(chn[0].dma, chn[0].channelId) &&
279  * (!IfxDma_isChannelTransactionEnabled(chn[0].dma, chn[0].channelId))) {
280  * // Dma is out of RESET and there is no hardware request enabled
281  * IfxDma_Dma_startChannelTransaction(&chn[0]);
282  * }
283  * \endcode
284  *
285  */
286 IFX_INLINE boolean IfxDma_isChannelReset(Ifx_DMA *dma, IfxDma_ChannelId channelId);
287 
288 /** \brief Reset the channel
289  * \param dma pointer to DMA module
290  * \param channelId DMA channel number
291  * \return None
292  *
293  * \code
294  * // Apply reset to the channel
295  * IfxDma_resetChannel(chn[0].dma, chn[0].channelId);
296  * \endcode
297  *
298  */
299 IFX_INLINE void IfxDma_resetChannel(Ifx_DMA *dma, IfxDma_ChannelId channelId);
300 
301 /** \} */
302 
303 /** \addtogroup IfxLld_Dma_Std_Channel_Transaction
304  * \{ */
305 
306 /******************************************************************************/
307 /*-------------------------Inline Function Prototypes-------------------------*/
308 /******************************************************************************/
309 
310 /** \brief Clear the channel transaction request lost flag status
311  * \param dma pointer to DMA module
312  * \param channelId DMA channel number
313  * \return None
314  *
315  * \code
316  * // Clear the channel transaction request lost flag status
317  * IfxDma_clearChannelTransactionRequestLost(chn[0].dma, chn[0].channelId);
318  * \endcode
319  *
320  */
322 
323 /** \brief Disable a DMA channel hardware transaction request
324  * \param dma pointer to DMA module
325  * \param channelId DMA channel number
326  * \return None
327  *
328  * A coding example can be found in \ref IfxDma_enableChannelTransaction
329  *
330  */
331 IFX_INLINE void IfxDma_disableChannelTransaction(Ifx_DMA *dma, IfxDma_ChannelId channelId);
332 
333 /** \brief Disable the generation of a channel transaction lost error interrupt
334  * \param dma pointer to DMA module
335  * \param channelId DMA channel number
336  * \return None
337  *
338  * \code
339  * // Disable the transaction request lost interrupt for given channel
340  * IfxDma_disableChannelTransactionLostError(chn[0].dma, chn[0].channelId);
341  * \endcode
342  *
343  */
345 
346 /** \brief Enable a DMA channel hardware transaction request
347  * \param dma pointer to DMA module
348  * \param channelId DMA channel number
349  * \return None
350  *
351  * \code
352  * unsigned *src = (unsigned *)((unsigned)&SRC_DMACH0.U + 4*NUM_CHANNELS);
353  * for(int chn=0; chn<NUM_CHANNELS; ++chn, ++src) {
354  * IfxSrc_setRequest(src);
355  * }
356  *
357  * // Do not restrict the hardware triggering to only one transaction
358  *
359  * IfxDma_setChannelContinuousMode(chn[0].dma, chn[0].channelId);
360  * IfxDma_setChannelContinuousMode(chn[1].dma, chn[1].channelId);
361  * IfxDma_setChannelContinuousMode(chn[2].dma, chn[2].channelId);
362  *
363  * // Check for end of transaction
364  *
365  * while(!(IfxDma_getAndClearChannelInterrupt(chn[0].dma, chn[0].channelId)));
366  *
367  * // Enable the hardware trigger for channel 3
368  * IfxDma_enableChannelTransaction(chn[3].dma, chn[3].channelId);
369  *
370  * // Disable the hardware trigger for channel 2
371  * IfxDma_disableChannelTransaction(chn[2].dma, chn[2].channelId);
372  * // Hardware triggers for second time
373  *
374  * unsigned *SRc = (unsigned *)((unsigned)&SRC_DMACH0.U + 4*NUM_CHANNELS);
375  * for(int chn=0; chn<NUM_CHANNELS; ++chn, ++src) {
376  * IfxSrc_setRequest(src);
377  * }
378  *
379  * // Restrict the hardware triggering to only one transaction
380  * IfxDma_setChannelSingleMode(chn[0].dma, chn[0].channelId);
381  * IfxDma_setChannelSingleMode(chn[1].dma, chn[1].channelId);
382  * \endcode
383  *
384  */
385 IFX_INLINE void IfxDma_enableChannelTransaction(Ifx_DMA *dma, IfxDma_ChannelId channelId);
386 
387 /** \brief Enable the generation of a channel transaction lost error interrupt
388  * \param dma pointer to DMA module
389  * \param channelId DMA channel number
390  * \return None
391  *
392  * \code
393  * // Enable the transaction request lost interrupt for given channel
394  * IfxDma_enableChannelTransactionLostError(chn[0].dma, chn[0].channelId);
395  * \endcode
396  *
397  */
399 
400 /** \brief Check the channel transaction request lost flag status
401  * \param dma pointer to DMA module
402  * \param channelId DMA channel number
403  * \return TRUE if the TRL is set
404  * FALSE if the TRL is not set
405  *
406  * \code
407  * boolean trlFlag;
408  *
409  * // Check whether the channel transaction request lost flag is set or not
410  * trlFlag = IfxDma_getChannelTransactionRequestLost(chn[0].dma, chn[0].channelId));
411  * \endcode
412  *
413  */
415 
416 /** \brief Converts DMA circular range to circular code
417  * \param range DMA circular range
418  * \return DMA circular code
419  */
421 
422 /** \brief Return the hardware transaction request status of a DMA channel
423  * \param dma pointer to DMA module
424  * \param channelId DMA channel number
425  * \return TRUE if the hardware transaction request is enabled
426  * FALSE if the hardware transaction request is disabled
427  *
428  * A coding example can be found in \ref IfxDma_isChannelReset
429  *
430  */
431 IFX_INLINE boolean IfxDma_isChannelTransactionEnabled(Ifx_DMA *dma, IfxDma_ChannelId channelId);
432 
433 /** \brief Return the status of a DMA channel (transaction pending)
434  * \param dma pointer to DMA module
435  * \param channelId DMA channel number
436  * \return TRUE if a transaction request for the given channel is pending
437  *
438  * \code
439  * // check for the channel request pending with the channel
440  * if (IfxDma_isChannelTransactionPending(chn[0].dma, chn[0].channelId) == TRUE) {
441  * // There is channel request pending for channel 0
442  * result |= 0;
443  * }
444  * \endcode
445  *
446  */
447 IFX_INLINE boolean IfxDma_isChannelTransactionPending(Ifx_DMA *dma, IfxDma_ChannelId channelId);
448 
449 /** \brief Sets the sensitivity of the module to sleep signal
450  * \param dma pointer to DMA registers
451  * \param mode mode selection (enable/disable)
452  * \return None
453  */
454 IFX_INLINE void IfxDma_setSleepMode(Ifx_DMA *dma, IfxDma_SleepMode mode);
455 
456 /** \brief Request a DMA channel transaction
457  * \param dma pointer to DMA module
458  * \param channelId DMA channel number
459  * \return None
460  *
461  * A coding example can be found in \ref IfxDma_Dma_startChannelTransaction
462  *
463  */
464 IFX_INLINE void IfxDma_startChannelTransaction(Ifx_DMA *dma, IfxDma_ChannelId channelId);
465 
466 /** \} */
467 
468 /** \addtogroup IfxLld_Dma_Std_Move_Engine
469  * \{ */
470 
471 /******************************************************************************/
472 /*-------------------------Inline Function Prototypes-------------------------*/
473 /******************************************************************************/
474 
475 /** \brief Clear the DMA error status flags
476  * \param dma pointer to DMA module
477  * \param moveEngine pointer to the DMA move engine
478  * \param mask value holds the bits to clear or mask
479  * \return None
480  *
481  * \code
482  * // Clear the status of the error flags (as defined in _Impl/IfxDma_cfg.h)
483  * IfxDma_clearErrorFlags(chn[0].dma,IfxDma_MoveEngine_1,
484  * IFXDMA_ERROR_S | // move engine source error
485  * IFXDMA_ERROR_D | // move engine destination error
486  * IFXDMA_ERROR_SPB | // bus error on SPB
487  * IFXDMA_ERROR_SRI | // bus error on SRI
488  * IFXDMA_ERROR_RAM | // RAM error
489  * IFXDMA_ERROR_SLL | // safe linked list CRC checksum error
490  * IFXDMA_ERROR_DLL); // failed linked list load error
491  * \endcode
492  *
493  */
494 IFX_INLINE void IfxDma_clearErrorFlags(Ifx_DMA *dma, IfxDma_MoveEngine moveEngine, uint32 mask);
495 
496 /** \brief Disable the generation of a Move engine destination error interrupt
497  * \param dma pointer to DMA module
498  * \param moveEngine pointer to the DMA move engine
499  * \return None
500  *
501  * A coding example can be found in \ref IfxDma_disableMoveEngineSourceError
502  *
503  */
505 
506 /** \brief Disable the generation of a Move engine source error interrupt
507  * \param dma pointer to DMA module
508  * \param moveEngine pointer to the DMA move engine
509  * \return None
510  *
511  * \code
512  * // Disable the move engine source and destination move errors
513  * IfxDma_disableMoveEngineSourceError(chn[0].dma,IfxDma_MoveEngine_1);
514  * IfxDma_disableMoveEngineDestinationError(chn[0].dma,IfxDma_MoveEngine_1);
515  * \endcode
516  *
517  */
519 
520 /** \brief Enable the generation of a Move engine destination error interrupt
521  * \param dma pointer to DMA module
522  * \param moveEngine pointer to the DMA move engine
523  * \return None
524  *
525  * A coding example can be found in \ref IfxDma_enableMoveEngineSourceError
526  *
527  */
529 
530 /** \brief Enable the generation of a Move engine source error interrupt
531  * \param dma pointer to DMA module
532  * \param moveEngine pointer to the DMA move engine
533  * \return None
534  *
535  * \code
536  * // Enable the move engine source and destination move errors
537  * IfxDma_enableMoveEngineSourceError(chn[0].dma,IfxDma_MoveEngine_1);
538  * IfxDma_enableMoveEngineDestinationError(chn[0].dma,IfxDma_MoveEngine_1);
539  * \endcode
540  *
541  */
543 
544 /** \brief Return the DMA error status flags
545  * \param dma pointer to DMA module
546  * \param moveEngine pointer to the DMA move engine
547  * \return the content of the DMA.ERRSR register
548  *
549  * \code
550  * uint32 errorFlags = 0;
551  *
552  * // Get the status of the error flags of move engine
553  * errorFlags = IfxDma_getErrorFlags(chn[0].dma,IfxDma_MoveEngine_1);
554  *
555  * if( errorFlags & IFXDMA_ERROR_S ) { // move engine source error
556  * }
557  *
558  * if( errorFlags & IFXDMA_ERROR_D ) { // move engine destination error
559  * // ...
560  * }
561  *
562  * if( errorFlags & IFXDMA_ERROR_SPB ) { // bus error on SPB
563  * // ...
564  * }
565  *
566  * if( errorFlags & IFXDMA_ERROR_SRI ) { // bus error on SRI
567  * // ...
568  * }
569  *
570  * if( errorFlags & IFXDMA_ERROR_RAM ) { // RAM error
571  * // ...
572  * }
573  *
574  * if( errorFlags & IFXDMA_ERROR_SLL ) { // safe linked list CRC checksum error
575  * // ...
576  * }
577  *
578  * if( errorFlags & IFXDMA_ERROR_DLL ) { // failed linked list load error
579  * // ...
580  * }
581  * \endcode
582  *
583  */
584 IFX_INLINE uint32 IfxDma_getErrorFlags(Ifx_DMA *dma, IfxDma_MoveEngine moveEngine);
585 
586 /** \} */
587 
588 /** \addtogroup IfxLld_Dma_Std_Channel_Configure
589  * \{ */
590 
591 /******************************************************************************/
592 /*-------------------------Inline Function Prototypes-------------------------*/
593 /******************************************************************************/
594 
595 /** \brief Get a channel source address
596  * \param dma pointer to DMA module
597  * \param channelId DMA channel number
598  * \return Actual channel destination address
599  *
600  * \code
601  * uint32 destAddr = IfxDma_getChannelDestinationAddress(chn[2].dma, chn[2].channelId);
602  *
603  * \endcode
604  *
605  */
607 
608 /** \brief Get a channel source address
609  * \param dma pointer to DMA module
610  * \param channelId DMA channel number
611  * \return Actual channel source address
612  *
613  * \code
614  * uint32 sourceAddr = IfxDma_getChannelSourceAddress(chn[2].dma, chn[2].channelId);
615  * \endcode
616  *
617  */
619 
620 /** \brief Return remaining DMA transfer count
621  * \param dma pointer to DMA module
622  * \param channelId DMA channel number
623  * \return Remaining DMA transfer count
624  *
625  * \code
626  * // Wait till transfer count (TCOUNT) becomes 0
627  *
628  * bool notFinished;
629  * do {
630  * notFinished = false;
631  * if( IfxDma_getChannelTransferCount(chn[0].dma, chn[0].channelId) ) {
632  * notFinished = true;
633  * break;
634  * }
635  * } while( notFinished );
636  * \endcode
637  *
638  */
640 
641 /** \brief get the time stamp
642  * \param dma pointer to DMA module
643  * \return the current time stamp
644  *
645  * \code
646  * uint32 timestamp = IfxDma_getTimestamp(chn[0].dma);
647  * \endcode
648  *
649  */
651 
652 /** \brief Configure the move count for each DMA channel transfer
653  * \param dma pointer to DMA module
654  * \param channelId DMA channel number
655  * \param blockMode value holds the number of moves with in a DMA transfer
656  * \return None
657  *
658  * A coding example can be found in \ref IfxDma_setChannelTransferCount
659  *
660  */
661 IFX_INLINE void IfxDma_setChannelBlockMode(Ifx_DMA *dma, IfxDma_ChannelId channelId, IfxDma_ChannelMove blockMode);
662 
663 /** \brief Configure a DMA channel to "continous transaction mode"
664  * After a transaction, the hardware request transaction remain enabled
665  * \param dma pointer to DMA module
666  * \param channelId DMA channel number
667  * \return None
668  *
669  * A coding example can be found in \ref IfxDma_enableChannelTransaction
670  *
671  */
672 IFX_INLINE void IfxDma_setChannelContinuousMode(Ifx_DMA *dma, IfxDma_ChannelId channelId);
673 
674 /** \brief Configure the destination address
675  * \param dma pointer to DMA module
676  * \param channelId DMA channel number
677  * \param address is the Initial address of the destination pointer
678  * \return None
679  *
680  * A coding example can be found in \ref IfxDma_setChannelSourceAddress
681  *
682  */
683 IFX_INLINE void IfxDma_setChannelDestinationAddress(Ifx_DMA *dma, IfxDma_ChannelId channelId, void *address);
684 
685 /** \brief Configure a DMA channel destination pointer
686  * \param dma pointer to DMA module
687  * \param channelId DMA channel number
688  * \param incStep Specifies the pointer incrementation step
689  * \param direction Specifies the incrementation direction
690  * \param size Specifies the size of the circular buffer
691  * \return None
692  *
693  * A coding example can be found in \ref IfxDma_setChannelSourceIncrementStep
694  *
695  */
697 
698 /** \brief Configure a DMA channel move
699  * \param dma pointer to DMA module
700  * \param channelId DMA channel number
701  * \param moveSize value holds the opcode or size of data of individual moves with in a DMA transfer
702  * \return None
703  *
704  * A coding example can be found in \ref IfxDma_setChannelTransferCount
705  *
706  */
707 IFX_INLINE void IfxDma_setChannelMoveSize(Ifx_DMA *dma, IfxDma_ChannelId channelId, IfxDma_ChannelMoveSize moveSize);
708 
709 /** \brief Configure a DMA channel shadow pointer
710  * \param dma pointer to DMA module
711  * \param channelId DMA channel number
712  * \param shadow Specifies the shadow pointer
713  * \return None
714  *
715  * \code
716  * // Push the shadow mode into double buffer
717  * IfxDma_setChannelShadow(chn[0].dma, chn[0].channelId,
718  * IfxDma_ChannelShadow_doubleSourceBufferingSwSwitch);
719  * \endcode
720  *
721  */
722 IFX_INLINE void IfxDma_setChannelShadow(Ifx_DMA *dma, IfxDma_ChannelId channelId, IfxDma_ChannelShadow shadow);
723 
724 /** \brief Configure a DMA channel to "single transaction mode"
725  * After a transaction, the hardware request transaction is disabled, and must be set by software again
726  * \param dma pointer to DMA module
727  * \param channelId DMA channel number
728  * \return None
729  *
730  * A coding example can be found in \ref IfxDma_enableChannelTransaction
731  *
732  */
733 IFX_INLINE void IfxDma_setChannelSingleMode(Ifx_DMA *dma, IfxDma_ChannelId channelId);
734 
735 /** \brief Configure a DMA channel to "single transaction mode"
736  * One transfer request starts a complete DMA transaction
737  * \param dma pointer to DMA module
738  * \param channelId DMA channel number
739  * \return None
740  *
741  * A coding example can be found in \ref IfxDma_setChannelTransferCount
742  *
743  */
745 
746 /** \brief Configure a DMA channel to "single transfer mode"
747  * A transfer request is required for each transfer
748  * \param dma pointer to DMA module
749  * \param channelId DMA channel number
750  * \return None
751  *
752  * A coding example can be found in \ref IfxDma_setChannelTransferCount
753  *
754  */
755 IFX_INLINE void IfxDma_setChannelSingleTransfer(Ifx_DMA *dma, IfxDma_ChannelId channelId);
756 
757 /** \brief Configure the source address
758  * \param dma pointer to DMA module
759  * \param channelId DMA channel number
760  * \param address is the Initial address of the source pointer
761  * \return None
762  *
763  * \code
764  * // Check for the end of current transaction and before trigger the channel request for
765  * // for another channel, re configure the source and destination addresses
766  *
767  * while(!(IfxDma_getAndClearChannelInterrupt(chn[1].dma, chn[1].channelId)));
768  *
769  * // Re-Program the source address for the channel 2
770  * IfxDma_setChannelSourceAddress(chn[2].dma, chn[2].channelId,Sadr);
771  *
772  * // Re-Program the destination address for channel 2
773  * IfxDma_setChannelDestinationAddress(chn[2].dma, chn[2].channelId,Dadr);
774  *
775  * // Start DMA transaction for channel 2
776  * IfxDma_Dma_startChannelTransaction(&chn[2]);
777  * \endcode
778  *
779  */
780 IFX_INLINE void IfxDma_setChannelSourceAddress(Ifx_DMA *dma, IfxDma_ChannelId channelId, const void *address);
781 
782 /** \brief Configure a DMA channel source pointer
783  * \param dma pointer to DMA module
784  * \param channelId DMA channel number
785  * \param incStep Specifies the pointer incrementation step
786  * \param direction Specifies the incrementation direction
787  * \param size Specifies the size of the circular buffer
788  * \return None
789  *
790  * \code
791  * // Re-program the source and destination circular buffer control fields
792  * IfxDma_setChannelSourceIncrementStep(chn[0].dma, chn[0].channelId, IfxDma_ChannelIncrementStep_2, IfxDma_ChannelIncrementDirection_negative, IfxDma_ChannelIncrementCircular_16);
793  *
794  * IfxDma_setChannelDestinationIncrementStep(chn[0].dma, chn[0].channelId, IfxDma_ChannelIncrementStep_2, IfxDma_ChannelIncrementDirection_negative, IfxDma_ChannelIncrementCircular_16);
795  * \endcode
796  *
797  */
799 
800 /** \brief Configure the move count of a DMA channel transaction
801  * \param dma pointer to DMA module
802  * \param channelId DMA channel number
803  * \param transferCount value holds the DMA transfers within a transaction (1..16383; 0 handled like 1 transaction)
804  * \return None
805  *
806  * \code
807  * // Start DMA transaction
808  * IfxDma_Dma_startChannelTransaction(&chn[0]);
809  *
810  * // Wait till end of transaction
811  * while(!(IfxDma_getAndClearChannelInterrupt(chn[0].dma, chn[0].channelId)));
812  *
813  * // Change the TREL configuration for channel 1
814  * IfxDma_setChannelTransferCount(chn[1].dma, chn[1].channelId,0x6);
815  *
816  * // Change the BLKM configuration for channel 1
817  * IfxDma_setChannelBlockMode(chn[1].dma, chn[1].channelId,IfxDma_ChannelMove_3);
818  *
819  * // Change the Move size configuration for channel 1
820  * IfxDma_setChannelMoveSize(chn[1].dma, chn[1].channelId,IfxDma_ChannelMoveSize_64bit);
821  *
822  * // Pull down the channel pending request after the first transfer is initiated
823  * IfxDma_setChannelSingleTransfer(chn[1].dma, chn[1].channelId);
824  *
825  * // Pull down the channel pending request after the transaction gets over
826  * IfxDma_setChannelSingleTransaction(chn[2].dma, chn[2].channelId);
827  *
828  * // Start DMA transaction
829  * IfxDma_Dma_startChannelTransaction(&chn[1]);
830  *
831  * // Start DMA transaction
832  * IfxDma_Dma_startChannelTransaction(&chn[2]);
833  * \endcode
834  *
835  */
836 IFX_INLINE void IfxDma_setChannelTransferCount(Ifx_DMA *dma, IfxDma_ChannelId channelId, uint32 transferCount);
837 
838 /** \brief Configure the shadow pointer register to read only
839  * \param dma pointer to DMA module
840  * \param channelId DMA channel number
841  * \return None
842  *
843  * \code
844  * // Disable the shadow mode to come out of double buffer mode
845  * IfxDma_writeChannelShadowDisable(chn[0].dma, chn[0].channelId);
846  * \endcode
847  *
848  */
849 IFX_INLINE void IfxDma_writeChannelShadowDisable(Ifx_DMA *dma, IfxDma_ChannelId channelId);
850 
851 /** \brief Configure the shadow pointer register to write-able
852  * \param dma pointer to DMA module
853  * \param channelId DMA channel number
854  * \return None
855  *
856  * \code
857  * // Enable the shadow mode to come out of double buffer mode
858  * IfxDma_writeChannelShadowEnable(chn[0].dma, chn[0].channelId);
859  * \endcode
860  *
861  */
862 IFX_INLINE void IfxDma_writeChannelShadowEnable(Ifx_DMA *dma, IfxDma_ChannelId channelId);
863 
864 /** \} */
865 
866 /** \addtogroup IfxLld_Dma_Std_Channel_Halt
867  * \{ */
868 
869 /******************************************************************************/
870 /*-------------------------Inline Function Prototypes-------------------------*/
871 /******************************************************************************/
872 
873 /** \brief Clear channel halt request and aknowledgement
874  * \param dma pointer to DMA module
875  * \param channelId DMA channel number
876  * \return None
877  *
878  * \code
879  * // Quit the halt mode of operation
880  * IfxDma_clearChannelHalt(chn[0].dma, chn[0].channelId);
881  * \endcode
882  *
883  */
884 IFX_INLINE void IfxDma_clearChannelHalt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
885 
886 /** \brief Get channel halt aknowledgement
887  * \param dma pointer to DMA module
888  * \param channelId DMA channel number
889  * \return halt aknowledgement
890  *
891  * \code
892  * // Check for the channel halt aknowledgement
893  * while(!(IfxDma_getChannelHalt(chn[0].dma, chn[0].channelId)));
894  * \endcode
895  *
896  */
897 IFX_INLINE boolean IfxDma_getChannelHalt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
898 
899 /** \brief setting channel halt request
900  * \param dma pointer to DMA module
901  * \param channelId DMA channel number
902  * \return None
903  *
904  * \code
905  * // Halt the channel processing
906  * IfxDma_setChannelHalt(chn[0].dma,chn[0].channelId);
907  * \endcode
908  *
909  */
910 IFX_INLINE void IfxDma_setChannelHalt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
911 
912 /** \} */
913 
914 /** \addtogroup IfxLld_Dma_Std_Double_Buffer
915  * \{ */
916 
917 /******************************************************************************/
918 /*-------------------------Inline Function Prototypes-------------------------*/
919 /******************************************************************************/
920 
921 /** \brief get information on buffer being read by software and clear the notification flag
922  * \param dma pointer to DMA module
923  * \param channelId DMA channel number
924  * \return TRUE if one of the buffers is being read by software
925  * FALSE if one of the buffers is already read by software
926  *
927  * \code
928  * // Check the buffer being read (Double buffer operation mode)
929  * while(!(IfxDma_getDoubleBufferRead(chn[0].dma, chn[0].channelId)));
930  * \endcode
931  *
932  */
933 IFX_INLINE boolean IfxDma_getDoubleBufferRead(Ifx_DMA *dma, IfxDma_ChannelId channelId);
934 
935 /** \brief get Double buffer selection
936  * \param dma pointer to DMA module
937  * \param channelId channelId DMA channel number
938  * \return TRUE if buffer 1 is being filled
939  * FALSE if buffer 0 is being filled
940  *
941  * \code
942  * boolean buffer_being_filled;
943  *
944  * // Check the buffer being filled (Double buffer operation mode)
945  * buffer_being_filled = IfxDma_getDoubleBufferSelection(chn[0].dma, chn[0].channelId));
946  * \endcode
947  *
948  */
949 IFX_INLINE boolean IfxDma_getDoubleBufferSelection(Ifx_DMA *dma, IfxDma_ChannelId channelId);
950 
951 /** \brief keeps the double buffer active
952  * \param dma pointer to DMA module
953  * \param channelId DMA channel number
954  * \return None
955  *
956  * \code
957  * IfxDma_keepDoubleBufferActive(chn[0].dma, chn[0].channelId);
958  * \endcode
959  *
960  */
961 IFX_INLINE void IfxDma_keepDoubleBufferActive(Ifx_DMA *dma, IfxDma_ChannelId channelId);
962 
963 /** \brief Double buffer switch application
964  * \param dma pointer to DMA module
965  * \param channelId DMA channel number
966  * \return None
967  *
968  * \code
969  * // Apply software buffer switch
970  * IfxDma_switchDoubleBuffer(chn[0].dma, chn[0].channelId);
971  * \endcode
972  *
973  */
974 IFX_INLINE void IfxDma_switchDoubleBuffer(Ifx_DMA *dma, IfxDma_ChannelId channelId);
975 
976 /** \} */
977 
978 /** \addtogroup IfxLld_Dma_Std_Interrupts
979  * \{ */
980 
981 /******************************************************************************/
982 /*-------------------------Inline Function Prototypes-------------------------*/
983 /******************************************************************************/
984 
985 /** \brief Clear a channel transfer interrupt flag
986  * \param dma pointer to DMA module
987  * \param channelId channel for which the interrupt flag should be cleared
988  * \return None
989  *
990  * see Dma.INTSR
991  *
992  */
993 IFX_INLINE void IfxDma_clearChannelInterrupt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
994 
995 /** \brief Disable channel interrupt trigger
996  * \param dma pointer to DMA module
997  * \param channelId DMA channel number
998  * \return None
999  *
1000  * \code
1001  * IfxDma_disableChannelInterrupt(chn[0].dma, chn[0].channelId);
1002  * \endcode
1003  *
1004  */
1005 IFX_INLINE void IfxDma_disableChannelInterrupt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1006 
1007 /** \brief Enable channel interrupt trigger
1008  * \param dma pointer to DMA module
1009  * \param channelId DMA channel number
1010  * \return None
1011  *
1012  * \code
1013  * IfxDma_enableChannelInterrupt(chn[0].dma, chn[0].channelId);
1014  * \endcode
1015  *
1016  */
1017 IFX_INLINE void IfxDma_enableChannelInterrupt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1018 
1019 /** \brief Return and clear a channel transfer interrupt flag
1020  * The flag is automatically cleared with the call to this function
1021  * \param dma pointer to DMA module
1022  * \param channelId DMA channel number
1023  * \return TRUE if the interrupt flag is set
1024  * FALSE if the interrupt flag is not set
1025  *
1026  * \code
1027  * // wait for the end of transaction for intended channel by checking the channel interrupt flag
1028  * // and clear it once it is set and checked
1029  *
1030  * // Wait till end of the transaction
1031  * while(!(IfxDma_getAndClearChannelInterrupt(chn[2].dma, chn[2].channelId)));
1032  * \endcode
1033  *
1034  */
1035 IFX_INLINE boolean IfxDma_getAndClearChannelInterrupt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1036 
1037 /** \brief Returns and clears the pattern detection interrupt flag
1038  * \param dma pointer to DMA module
1039  * \param channelId DMA channel number
1040  * \return TRUE if pattern detection for a given channel is found
1041  * FALSE if pattern detection for a given channel is not found
1042  *
1043  * \code
1044  * // wait till pattern match is found for given channel
1045  * // and clear it once it is set and checked
1046  *
1047  * // Wait for the pattern detection
1048  * while(!(IfxDma_getAndClearChannelPatternDetectionInterrupt(chn[0].dma, chn[0].channelId)));
1049  * \endcode
1050  *
1051  */
1053 
1054 /** \brief Returns and clears the status of channel wrap destination buffer interrupt trigger flag
1055  * \param dma pointer to DMA module
1056  * \param channelId DMA channel number
1057  * \return TRUE if wrap destination buffer interrupt trigger flag is set
1058  * FALSE if wrap destination buffer interrupt trigger flag is not set or get cleared already
1059  *
1060  * \code
1061  * // wait for the destination buffer wrap interrupt flag
1062  * // and clear it once it is set and checked
1063  * boolean destinationWrapFlag;
1064  *
1065  * destinationWrapFlag = IfxDma_getAndClearChannelWrapDestinationBufferInterrupt(chn[0].dma, chn[0].channelId);
1066  * \endcode
1067  *
1068  */
1070 
1071 /** \brief Returns and clears the status of channel wrap source buffer interrupt trigger flag
1072  * \param dma pointer to DMA module
1073  * \param channelId DMA channel number
1074  * \return TRUE if wrap source buffer interrupt trigger flag is set
1075  * FALSE if wrap source buffer interrupt trigger flag is not set or get cleared already
1076  *
1077  * \code
1078  * // wait for the source buffer wrap interrupt flag
1079  * // and clear it once it is set and checked
1080  * boolean sourceWrapFlag;
1081  *
1082  * sourceWrapFlag = IfxDma_getAndClearChannelWrapSourceBufferInterrupt(chn[0].dma, chn[0].channelId);
1083  * \endcode
1084  *
1085  */
1087 
1088 /** \brief Return a channel transfer interrupt flag
1089  * \param dma pointer to DMA module
1090  * \param channelId channel for which the interrupt flag should be returned
1091  * \return TRUE if the interrupt flag is set
1092  * FALSE if the interrupt flag is not set
1093  *
1094  * see Dma.INTSR
1095  *
1096  */
1097 IFX_INLINE boolean IfxDma_getChannelInterrupt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1098 
1099 /** \brief Returns whether the old value of pattern detection corresponding pattern comparison operation found a pattern match in previous DMA * read move or not
1100  * \param dma pointer to DMA module
1101  * \param channelId DMA channel number
1102  * \return TRUE if corresponding pattern comparison operation found a pattern match in previous DMA read move or not
1103  * FALSE if corresponding pattern comparison operation did not find a pattern match in previous DMA read move
1104  *
1105  * \code
1106  * boolean patternDetectOldVal;
1107  *
1108  * // Check the old value of the pattern detection
1109  * patternDetectOldVal = IfxDma_getChannelPatternDetectionOldValue(chn[0].dma, chn[0].channelId);
1110  * \endcode
1111  *
1112  */
1114 
1115 /** \brief Returns the SRC pointer for given DMA channel
1116  * \param dma pointer to DMA module
1117  * \param channelId DMA channel number
1118  * \return SRC pointer for given DMA channel
1119  *
1120  * \code
1121  *
1122  * \endcode
1123  *
1124  */
1125 IFX_INLINE volatile Ifx_SRC_SRCR *IfxDma_getSrcPointer(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1126 
1127 /** \brief Setting of channel interrupt service request by software
1128  * \param dma pointer to DMA module
1129  * \param channelId DMA channel number
1130  * \return None
1131  *
1132  * \code
1133  * // Set the channel interrupt service request through software
1134  * IfxDma_setChannelInterruptServiceRequest(chn[0].dma, chn[0].channelId);
1135  * \endcode
1136  *
1137  */
1139 
1140 /** \} */
1141 
1142 /******************************************************************************/
1143 /*---------------------Inline Function Implementations------------------------*/
1144 /******************************************************************************/
1145 
1147 {
1148  dma->TSR[channelId].B.HLTCLR = 1;
1149 }
1150 
1151 
1153 {
1154  dma->CH[channelId].CHCSR.B.CICH = 1;
1155 }
1156 
1157 
1159 {
1160  dma->TSR[channelId].B.CTL = 1;
1161 }
1162 
1163 
1164 IFX_INLINE void IfxDma_clearErrorFlags(Ifx_DMA *dma, IfxDma_MoveEngine moveEngine, uint32 mask)
1165 {
1166  dma->BLK0.CLRE.U = mask;
1167 }
1168 
1169 
1171 {
1172  dma->CH[channelId].ADICR.B.INTCT &= ~(1 << 1); // TODO: should we define a special bitmask for this bit manipulation?
1173 }
1174 
1175 
1177 {
1178  dma->TSR[channelId].B.DCH = 1;
1179 }
1180 
1181 
1183 {
1184  dma->CH[channelId].ADICR.B.ETRL = 0;
1185 }
1186 
1187 
1189 {
1190  dma->BLK0.EER.B.EDER = 0;
1191 }
1192 
1193 
1195 {
1196  dma->BLK0.EER.B.ESER = 0;
1197 }
1198 
1199 
1201 {
1202  dma->CH[channelId].ADICR.B.INTCT |= (1 << 1); // TODO: should we define a special bitmask for this bit manipulation?
1203 }
1204 
1205 
1207 {
1208  dma->TSR[channelId].B.ECH = 1;
1209 }
1210 
1211 
1213 {
1214  dma->CH[channelId].ADICR.B.ETRL = 1;
1215 }
1216 
1217 
1219 {
1220  dma->BLK0.EER.B.EDER = 1;
1221 }
1222 
1223 
1225 {
1226  dma->BLK0.EER.B.ESER = 1;
1227 }
1228 
1229 
1231 {
1232  boolean result;
1233 
1234  result = dma->CH[channelId].CHCSR.B.ICH != 0;
1235 
1236  if (result == 1)
1237  {
1238  dma->CH[channelId].CHCSR.B.CICH = TRUE;
1239  }
1240 
1241  return result;
1242 }
1243 
1244 
1246 {
1247  boolean result;
1248 
1249  result = dma->CH[channelId].CHCSR.B.IPM != 0;
1250 
1251  if (result == 1)
1252  {
1253  dma->CH[channelId].CHCSR.B.CICH = TRUE;
1254  }
1255 
1256  return result;
1257 }
1258 
1259 
1261 {
1262  boolean result;
1263 
1264  result = dma->CH[channelId].CHCSR.B.WRPD != 0;
1265 
1266  if (result == 1)
1267  {
1268  dma->CH[channelId].CHCSR.B.CWRP = TRUE;
1269  }
1270 
1271  return result;
1272 }
1273 
1274 
1276 {
1277  boolean result;
1278 
1279  result = dma->CH[channelId].CHCSR.B.WRPS != 0;
1280 
1281  if (result == 1)
1282  {
1283  dma->CH[channelId].CHCSR.B.CWRP = TRUE;
1284  }
1285 
1286  return result;
1287 }
1288 
1289 
1291 {
1292  return dma->CH[channelId].DADR.U;
1293 }
1294 
1295 
1296 IFX_INLINE boolean IfxDma_getChannelHalt(Ifx_DMA *dma, IfxDma_ChannelId channelId)
1297 {
1298  return dma->TSR[channelId].B.HLTACK != 0;
1299 }
1300 
1301 
1303 {
1304  boolean result;
1305 
1306  result = dma->CH[channelId].CHCSR.B.ICH;
1307 
1308  return result;
1309 }
1310 
1311 
1313 {
1314  return dma->CH[channelId].CHCSR.B.LXO != 0;
1315 }
1316 
1317 
1319 {
1320  return dma->CH[channelId].SADR.U;
1321 }
1322 
1323 
1325 {
1326  return dma->TSR[channelId].B.TRL != 0;
1327 }
1328 
1329 
1331 {
1332  return dma->CH[channelId].CHCSR.B.TCOUNT;
1333 }
1334 
1335 
1337 {
1338  return (IfxDma_ChannelIncrementCircular)(31 - __clz((uint32)range));
1339 }
1340 
1341 
1343 {
1344  boolean result;
1345 
1346  result = dma->CH[channelId].CHCSR.B.FROZEN != 0;
1347 
1348  if (result == 1)
1349  {
1350  dma->CH[channelId].CHCSR.B.FROZEN = FALSE;
1351  }
1352 
1353  return result;
1354 }
1355 
1356 
1358 {
1359  return dma->CH[channelId].CHCSR.B.BUFFER != 0;
1360 }
1361 
1362 
1364 {
1365  return dma->BLK0.ERRSR.U;
1366 }
1367 
1368 
1369 IFX_INLINE volatile Ifx_SRC_SRCR *IfxDma_getSrcPointer(Ifx_DMA *dma, IfxDma_ChannelId channelId)
1370 {
1371  // only a single DMA available, therefore no check for the dma pointer required
1372  return &MODULE_SRC.DMA.DMA[0].CH[channelId];
1373 }
1374 
1375 
1377 {
1378  return dma->TIME.U;
1379 }
1380 
1381 
1382 IFX_INLINE boolean IfxDma_isChannelReset(Ifx_DMA *dma, IfxDma_ChannelId channelId)
1383 {
1384  return dma->TSR[channelId].B.RST != 0;
1385 }
1386 
1387 
1389 {
1390  return dma->TSR[channelId].B.HTRE != 0;
1391 }
1392 
1393 
1395 {
1396  return dma->TSR[channelId].B.CH != 0;
1397 }
1398 
1399 
1401 {
1402  dma->CH[channelId].CHCSR.U = 0U << IFX_DMA_CH_CHCSR_FROZEN_OFF;
1403 }
1404 
1405 
1406 IFX_INLINE void IfxDma_resetChannel(Ifx_DMA *dma, IfxDma_ChannelId channelId)
1407 {
1408  dma->TSR[channelId].B.RST = 1;
1409 }
1410 
1411 
1413 {
1414  dma->CH[channelId].CHCFGR.B.BLKM = blockMode;
1415 }
1416 
1417 
1419 {
1420  dma->CH[channelId].CHCFGR.B.CHMODE = 1;
1421 }
1422 
1423 
1424 IFX_INLINE void IfxDma_setChannelDestinationAddress(Ifx_DMA *dma, IfxDma_ChannelId channelId, void *address)
1425 {
1426  dma->CH[channelId].DADR.U = (uint32)address;
1427 }
1428 
1429 
1431 {
1432  Ifx_DMA_BLK_ME_ADICR adicr;
1433  adicr.U = dma->CH[channelId].ADICR.U;
1434  adicr.B.DMF = incStep;
1435  adicr.B.INCD = direction;
1436  adicr.B.CBLD = size;
1437  dma->CH[channelId].ADICR.U = adicr.U;
1438 }
1439 
1440 
1442 {
1443  dma->TSR[channelId].B.HLTREQ = 1;
1444 }
1445 
1446 
1448 {
1449  dma->CH[channelId].CHCSR.B.SIT = 1;
1450 }
1451 
1452 
1454 {
1455  dma->CH[channelId].CHCFGR.B.CHDW = moveSize;
1456 }
1457 
1458 
1460 {
1461  dma->CH[channelId].ADICR.B.SHCT = shadow;
1462 }
1463 
1464 
1466 {
1467  dma->CH[channelId].CHCFGR.B.CHMODE = 0;
1468 }
1469 
1470 
1472 {
1473  dma->CH[channelId].CHCFGR.B.RROAT = 1;
1474 }
1475 
1476 
1478 {
1479  dma->CH[channelId].CHCFGR.B.RROAT = 0;
1480 }
1481 
1482 
1483 IFX_INLINE void IfxDma_setChannelSourceAddress(Ifx_DMA *dma, IfxDma_ChannelId channelId, const void *address)
1484 {
1485  dma->CH[channelId].SADR.U = (uint32)address;
1486 }
1487 
1488 
1490 {
1491  Ifx_DMA_BLK_ME_ADICR adicr;
1492  adicr.U = dma->CH[channelId].ADICR.U;
1493  adicr.B.SMF = incStep;
1494  adicr.B.INCS = direction;
1495  adicr.B.CBLS = size;
1496  dma->CH[channelId].ADICR.U = adicr.U;
1497 }
1498 
1499 
1500 IFX_INLINE void IfxDma_setChannelTransferCount(Ifx_DMA *dma, IfxDma_ChannelId channelId, uint32 transferCount)
1501 {
1502  dma->CH[channelId].CHCFGR.B.TREL = transferCount;
1503 }
1504 
1505 
1507 {
1509  IfxScuWdt_clearCpuEndinit(passwd);
1510  dma->CLC.B.EDIS = mode;
1511  IfxScuWdt_setCpuEndinit(passwd);
1512 }
1513 
1514 
1516 {
1517  dma->CH[channelId].CHCSR.B.SCH = 1;
1518 }
1519 
1520 
1522 {
1523  dma->CH[channelId].CHCSR.B.SWB = 1;
1524 }
1525 
1526 
1528 {
1529  dma->CH[channelId].ADICR.B.SHCT &= ~(3 << 2);
1530 }
1531 
1532 
1534 {
1535  dma->CH[channelId].ADICR.B.SHCT |= (1 << 2);
1536  dma->CH[channelId].ADICR.B.SHCT &= ~(1 << 3);
1537 }
1538 
1539 
1540 #endif /* IFXDMA_H */