iLLD_TC22x  1.0
IfxMtu.c
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1 /**
2  * \file IfxMtu.c
3  * \brief MTU basic functionality
4  *
5  * \version iLLD_1_0_0_11_0
6  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  *
24  */
25 
26 /******************************************************************************/
27 /*----------------------------------Includes----------------------------------*/
28 /******************************************************************************/
29 
30 #include "IfxMtu.h"
31 
32 /** \addtogroup IfxLld_Mtu_Std_Utility
33  * \{ */
34 
35 /******************************************************************************/
36 /*-----------------------Private Function Prototypes--------------------------*/
37 /******************************************************************************/
38 
39 /** \brief API to wait for requested tower depth.
40  * \param towerDepth tower depth of MBIST Ram
41  * \param numInstructions number of instructions
42  * \param mbistSel Memory Selection
43  * \return None
44  */
45 static void IfxMtu_waitForMbistDone(uint32 towerDepth, uint8 numInstructions, IfxMtu_MbistSel mbistSel);
46 
47 /** \} */
48 
49 /******************************************************************************/
50 /*-------------------------Function Implementations---------------------------*/
51 /******************************************************************************/
52 
53 void IfxMtu_clearErrorTracking(IfxMtu_MbistSel mbistSel)
54 {
55  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
56  mc->ECCD.U |= (1 << IFX_MC_ECCD_TRC_OFF);
57 }
58 
59 
60 void IfxMtu_clearSram(IfxMtu_MbistSel mbistSel)
61 {
62  uint8 isEndInitEnabled = 0;
63  uint16 password = 0;
64 
65  password = IfxScuWdt_getSafetyWatchdogPassword();
66 
67  /* Check if the Endinit is cleared by application. If not, then handle it internally inside teh function.*/
68  if (IfxScuWdt_getSafetyWatchdogEndInit() == 1U)
69  {
70  /* Clear EndInit */
71  IfxScuWdt_clearSafetyEndinit(password);
72  isEndInitEnabled = 1;
73  }
74 
75  IfxMtu_clearSramStart(mbistSel);
76 
77  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
78  IfxScuWdt_setSafetyEndinit(password);
79 
80  /* wait for the end of the fill operation */
81  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
82  IfxMtu_waitForMbistDone(IfxMtu_sramTable[mbistSel].mbistDelay, 1, mbistSel);
83  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, mc->MSTATUS.B.DONE != 0);
84 
85  while (!IfxMtu_isMbistDone(mbistSel))
86  {
87  __nop();
88  }
89 
90  /* Clear EndInit */
91  IfxScuWdt_clearSafetyEndinit(password);
92 
93  IfxMtu_clearSramContinue(mbistSel);
94 
95  if (isEndInitEnabled == 1)
96  {
97  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
98  IfxScuWdt_setSafetyEndinit(password);
99  }
100 }
101 
102 
103 void IfxMtu_clearSramContinue(IfxMtu_MbistSel mbistSel)
104 {
105  /* Before clearing the ECC error flags we've to issue a dummy SRAM access to get a valid memory output */
106  IfxMtu_readSramAddress(mbistSel, 0x0000);
107 
108  /* Note: a SMU alarm will be flagged HERE if the wrong ECC has been written! */
109  IfxMtu_disableMbistShell(mbistSel);
110 
111  /* for auto-init memories: wait for the end of the clear operation */
112  while (IfxMtu_isAutoInitRunning(mbistSel))
113  {}
114 }
115 
116 
117 void IfxMtu_clearSramStart(IfxMtu_MbistSel mbistSel)
118 {
119  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
120 
121  IfxMtu_enableMbistShell(mbistSel);
122 
123  /* for auto-init memories: wait for the end of the clear operation */
124  while (IfxMtu_isAutoInitRunning(mbistSel))
125  {}
126 
127  /* write valid ECC code for all-zero data into RDBFL registers */
128  {
129  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, mbistSel < IFXMTU_NUM_MBIST_TABLE_ITEMS);
130  const IfxMtu_SramItem *item = (IfxMtu_SramItem *)&IfxMtu_sramTable[mbistSel];
131 
132  uint8 numBlocks = item->numBlocks;
133  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, numBlocks > 0);
134 
135  uint16 dataSize = item->dataSize;
136  uint8 eccSize = item->eccSize;
137  uint32 eccInvPos0 = dataSize + item->eccInvPos0;
138  uint32 eccInvPos1 = dataSize + item->eccInvPos1;
139 
140  uint32 memSize = dataSize + eccSize;
141 
142  uint32 bitPos = 0;
143  uint32 wordIx = 0;
144  uint16 data = 0;
145  /* de-serialize data stream into 16bit packets */
146  uint32 mem;
147 
148  for (mem = 0; mem < numBlocks; ++mem)
149  {
150  uint32 i;
151 
152  for (i = 0; i < memSize; ++i)
153  {
154  if ((i == eccInvPos0) || (i == eccInvPos1))
155  {
156  data |= (1 << bitPos);
157  }
158 
159  ++bitPos;
160 
161  if (bitPos >= 16)
162  {
163  mc->RDBFL[wordIx++].U = data;
164  bitPos = 0;
165  data = 0;
166  }
167  }
168  }
169 
170  /* final word? */
171  if (bitPos != 0)
172  {
173  mc->RDBFL[wordIx].U = data;
174  }
175  }
176 
177  /* start fill operation */
178  uint16 mcontrolMask = 0x4000; /* set USERED flag */
179  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DINIT_OFF) | (1 << IFX_MC_MCONTROL_START_OFF); /* START = DINIT = 1 */
180  mc->MCONTROL.U = mcontrolMask | (0 << IFX_MC_MCONTROL_DINIT_OFF) | (1 << IFX_MC_MCONTROL_DINIT_OFF); /* START = 0 */
181 }
182 
183 
184 void IfxMtu_disableMbistShell(IfxMtu_MbistSel mbistSel)
185 {
186  volatile uint32 *mtuMemtest = (volatile uint32 *)((uint32)&MTU_MEMTEST0 + 4 * (mbistSel >> 5));
187  uint32 mask = 1 << (mbistSel & 0x1f);
188  *mtuMemtest &= ~mask;
189 }
190 
191 
192 void IfxMtu_enableErrorTracking(IfxMtu_MbistSel mbistSel, boolean enable)
193 {
194  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
195 
196  if (enable == FALSE)
197  {
198  mc->ECCS.U &= ~(1 << IFX_MC_ECCS_TRE_OFF);
199  }
200  else
201  {
202  mc->ECCS.U |= (1 << IFX_MC_ECCS_TRE_OFF);
203  }
204 }
205 
206 
207 void IfxMtu_enableMbistShell(IfxMtu_MbistSel mbistSel)
208 {
209  volatile uint32 *mtuMemtest = (volatile uint32 *)((uint32)&MTU_MEMTEST0 + 4 * (mbistSel >> 5));
210  uint32 mask = 1 << (mbistSel & 0x1f);
211  *mtuMemtest |= mask;
212 }
213 
214 
215 uint32 IfxMtu_getSystemAddress(IfxMtu_MbistSel mbistSel, Ifx_MC_ETRR trackedSramAddress)
216 {
217  uint32 sramAddress = trackedSramAddress.B.ADDR;
218  uint32 mbi = trackedSramAddress.B.MBI;
219  uint32 systemAddress = 0;
220 
221  switch (mbistSel)
222  {
223  case IfxMtu_MbistSel_cpu0Pspr:
224  systemAddress = 0x70100000 | ((sramAddress << 3) | ((mbi & 1) << 2));
225  break;
226 
227  case IfxMtu_MbistSel_cpu0Dspr:
228  systemAddress = 0x70000000 | ((sramAddress << 4) | ((mbi & 3) << 2));
229  break;
230 
231  default:
232  systemAddress = 0; /* unsupported address descrambling */
233  }
234 
235  return systemAddress;
236 }
237 
238 
239 uint8 IfxMtu_getTrackedSramAddresses(IfxMtu_MbistSel mbistSel, Ifx_MC_ETRR *trackedSramAddresses)
240 {
241  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
242  uint8 validFlags = (mc->ECCD.U >> IFX_MC_ECCD_VAL_OFF) & IFX_MC_ECCD_VAL_MSK;
243  uint8 numTrackedAddresses = 0;
244  int i;
245 
246 #if IFX_MC_ECCD_VAL_LEN > IFXMTU_MAX_TRACKED_ADDRESSES
247 # error "Unexpected size of VAL mask"
248 #endif
249 
250  for (i = 0; i < IFXMTU_MAX_TRACKED_ADDRESSES; ++i)
251  {
252  if (validFlags & (1 << i))
253  {
254  trackedSramAddresses[numTrackedAddresses].U = mc->ETRR[i].U;
255  ++numTrackedAddresses;
256  }
257  }
258 
259  return numTrackedAddresses;
260 }
261 
262 
263 boolean IfxMtu_isAutoInitRunning(IfxMtu_MbistSel mbistSel)
264 {
265  volatile uint32 *mtuMemstat = (volatile uint32 *)((uint32)&MTU_MEMSTAT0 + 4 * (mbistSel >> 5));
266  uint32 mask = 1 << (mbistSel & 0x1f);
267  return (*mtuMemstat & mask) != 0;
268 }
269 
270 
271 boolean IfxMtu_isErrorTrackingEnabled(IfxMtu_MbistSel mbistSel)
272 {
273  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
274  return mc->ECCS.B.TRE ? TRUE : FALSE;
275 }
276 
277 
278 boolean IfxMtu_isErrorTrackingOverflow(IfxMtu_MbistSel mbistSel)
279 {
280  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
281  return mc->ECCD.B.EOV ? TRUE : FALSE;
282 }
283 
284 
285 boolean IfxMtu_isMbistDone(IfxMtu_MbistSel mbistSel)
286 {
287  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
288  uint16 status;
289 
290  status = mc->MSTATUS.U;
291  return (boolean)(status & 0x01);
292 }
293 
294 
295 void IfxMtu_readSramAddress(IfxMtu_MbistSel mbistSel, uint16 sramAddress)
296 {
297  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
298 
299  /* configure MBIST for single read opeation */
300  uint16 mcontrolMask = 0x4000; /* set USERED flag */
301  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DIR_OFF);
302  mc->CONFIG0.U = (1 << IFX_MC_CONFIG0_NUMACCS_OFF) | (1 << IFX_MC_CONFIG0_ACCSTYPE_OFF); /* 1 read access */
303  mc->CONFIG1.U = 0; /* ensure that linear scrambling is used */
304 
305  /* Set the address to be read (RAEN = 0) */
306  mc->RANGE.U = sramAddress;
307 
308  /* Start operation */
309  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DIR_OFF) | (1 << IFX_MC_MCONTROL_START_OFF);
310  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DIR_OFF);
311 
312  /* wait for the end of the fill operation */
313  IfxMtu_waitForMbistDone(256, 1, mbistSel);
314 
315  while (!IfxMtu_isMbistDone(mbistSel))
316  {
317  __nop();
318  }
319 }
320 
321 
322 uint8 IfxMtu_runCheckerBoardTest(IfxMtu_MbistSel mbistSel, uint8 rangeSel, uint8 rangeAddrUp, uint8 rangeAddrLow, uint16 *errorAddr, uint32 numberRedundancyLines)
323 {
324  /* Select MBIST Memory Controller:
325  * Ifx_MC is a type describing structure of MBIST Memory Controller
326  * registers defined in IfxMc_regdef.h file - MC object */
327  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
328  uint32 configCheckerBoardSequence[4] = {
329  0x08001000, //up /lin/w0
330  0x08001001, //up /lin/r0
331  0x00011000, //down/lin/w1
332  0x00011001
333  }; //down/lin/r1
334  uint16 password = 0;
335  uint8 retVal = 0U;
336  uint8 testStep;
337  uint8 isEndInitEnabled = 0;
338  password = IfxScuWdt_getSafetyWatchdogPassword();
339 
340  /* Check if the Endinit is cleared by application. If not, then handle it internally inside teh function.*/
341  if (IfxScuWdt_getSafetyWatchdogEndInit() == 1U)
342  {
343  /* Clear EndInit */
344  IfxScuWdt_clearSafetyEndinit(password);
345  isEndInitEnabled = 1;
346  }
347 
348  /* Enable MBIST Memory Controller */
349  IfxMtu_enableMbistShell(mbistSel);
350 
351  /* for auto-init memories: wait for the end of the clear operation */
352  while (IfxMtu_isAutoInitRunning(mbistSel))
353  {}
354 
355  /* Set the range register */
356  mc->RANGE.U = (rangeSel << 15) | (rangeAddrUp << 7) | (rangeAddrLow << 0);
357 
358  /* Run the test */
359  for (testStep = 0; testStep < 4; ++testStep)
360  {
361  mc->CONFIG0.U = configCheckerBoardSequence[testStep] & 0x0000FFFF;
362  mc->CONFIG1.U = (configCheckerBoardSequence[testStep] & 0xFFFF0000) >> 16;
363  mc->MCONTROL.U = numberRedundancyLines ? 0x30c9 : 0x00c9; // bit and row toggle
364  mc->MCONTROL.U = numberRedundancyLines ? 0x30c8 : 0x00c8; // MCONTROL.B.START will generate a RMW which is too long for small SRAMs!
365 
366  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
367  IfxScuWdt_setSafetyEndinit(password);
368 
369  /* wait for the end of the fill operation */
370  IfxMtu_waitForMbistDone(IfxMtu_sramTable[mbistSel].mbistDelay, 4, mbistSel);
371  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, mc->MSTATUS.B.DONE != 0);
372 
373  while (!IfxMtu_isMbistDone(mbistSel))
374  {
375  __nop();
376  }
377 
378  /* Clear EndInit Again */
379  IfxScuWdt_clearSafetyEndinit(password);
380 
381  /* Check the Fail Status */
382  if (mc->MSTATUS.B.FAIL)
383  {
384  /* Test has failed, check if any un-correctable error */
385  if (mc->ECCD.B.UERR)
386  {
387  /* Read Error tracking register and return saying test failed */
388  *errorAddr = mc->ETRR[0].U;
389  retVal = 1U;
390  break;
391  }
392  }
393  }
394 
395  /* Disable Memory Controller */
396 
397  IfxMtu_disableMbistShell(mbistSel);
398 
399  while (IfxMtu_isAutoInitRunning(mbistSel))
400  {}
401 
402  if (isEndInitEnabled == 1)
403  {
404  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
405  IfxScuWdt_setSafetyEndinit(password);
406  }
407 
408  return retVal;
409 }
410 
411 
412 uint8 IfxMtu_runMarchUTest(IfxMtu_MbistSel mbistSel, uint8 rangeSel, uint8 rangeAddrUp, uint8 rangeAddrLow, uint16 *errorAddr)
413 {
414  /* Select MBIST Memory Controller:
415  * Ifx_MC is a type describing structure of MBIST Memory Controller
416  * registers defined in IfxMc_regdef.h file - MC object */
417  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
418  uint32 configMarchUSequence[6] = {
419  0x08001000, //up /lin/w0
420  0x08064005, //up /lin/r0->w1->r1->w0
421  0x08022001, //up /lin/r0->w1
422  0x00094005, //down/lin/r1->w0->r0->w1
423  0x00012001, //down/lin/r1->w0
424  0x00001001
425  }; //down/lin/r0
426  uint16 password = 0;
427  uint8 retVal = 0U;
428  uint8 testStep;
429  uint8 isEndInitEnabled = 0;
430  password = IfxScuWdt_getSafetyWatchdogPassword();
431 
432  /* Check if the Endinit is cleared by application. If not, then handle it internally inside teh function.*/
433  if (IfxScuWdt_getSafetyWatchdogEndInit() == 1U)
434  {
435  /* Clear EndInit */
436  IfxScuWdt_clearSafetyEndinit(password);
437  isEndInitEnabled = 1;
438  }
439 
440  /* Enable MBIST Memory Controller */
441  IfxMtu_enableMbistShell(mbistSel);
442 
443  /* for auto-init memories: wait for the end of the clear operation */
444  while (IfxMtu_isAutoInitRunning(mbistSel))
445  {}
446 
447  /* Set the range register */
448  mc->RANGE.U = (rangeSel << 15) | (rangeAddrUp << 7) | (rangeAddrLow << 0);
449 
450  /* Run the test */
451  for (testStep = 0; testStep < 6; ++testStep)
452  {
453  mc->CONFIG0.U = configMarchUSequence[testStep] & 0x0000FFFF;
454  mc->CONFIG1.U = (configMarchUSequence[testStep] & 0xFFFF0000) >> 16;
455  mc->MCONTROL.U = 0x0209;
456  mc->MCONTROL.B.START = 0;
457 
458  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
459  IfxScuWdt_setSafetyEndinit(password);
460 
461  /* wait for the end of the fill operation */
462  IfxMtu_waitForMbistDone(IfxMtu_sramTable[mbistSel].mbistDelay, 4, mbistSel);
463  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, mc->MSTATUS.B.DONE != 0);
464 
465  while (!IfxMtu_isMbistDone(mbistSel))
466  {
467  __nop();
468  }
469 
470  /* Clear EndInit Again */
471  IfxScuWdt_clearSafetyEndinit(password);
472 
473  /* Check the Fail Status */
474  if (mc->MSTATUS.B.FAIL)
475  {
476  /* Test has failed, check if any un-correctable error */
477  if (mc->ECCD.B.UERR)
478  {
479  /* Read Error tracking register and return saying test failed */
480  *errorAddr = mc->ETRR[0].U;
481  retVal = 1U;
482  break;
483  }
484  }
485  }
486 
487  /* Disable Memory Controller */
488  IfxMtu_disableMbistShell(mbistSel);
489 
490  /* for auto-init memories: wait for the end of the clear operation */
491  while (IfxMtu_isAutoInitRunning(mbistSel))
492  {}
493 
494  /* Restore the endinit state */
495  if (isEndInitEnabled == 1)
496  {
497  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
498  IfxScuWdt_setSafetyEndinit(password);
499  }
500 
501  return retVal;
502 }
503 
504 
505 uint8 IfxMtu_runNonDestructiveInversionTest(IfxMtu_MbistSel mbistSel, uint8 rangeSel, uint8 rangeAddrUp, uint8 rangeAddrLow, uint16 *errorAddr)
506 {
507  /* Select MBIST Memory Controller:
508  * Ifx_MC is a type describing structure of MBIST Memory Controller
509  * registers defined in IfxMc_regdef.h file - MC object */
510  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
511  uint16 password = 0;
512  uint8 retVal = 0U;
513  uint8 isEndInitEnabled = 0;
514  password = IfxScuWdt_getSafetyWatchdogPassword();
515 
516  /* Check if the Endinit is cleared by application. If not, then handle it internally inside teh function.*/
517  if (IfxScuWdt_getSafetyWatchdogEndInit() == 1U)
518  {
519  /* Clear EndInit */
520  IfxScuWdt_clearSafetyEndinit(password);
521  isEndInitEnabled = 1;
522  }
523 
524  /* Enable MBIST Memory Controller */
525  IfxMtu_enableMbistShell(mbistSel);
526 
527  /* for auto-init memories: wait for the end of the clear operation */
528  while (IfxMtu_isAutoInitRunning(mbistSel))
529  {}
530 
531  /* Configure Non-destructive Inversion test */
532  mc->CONFIG0.U = 0x4005; //NUMACCS=4, ACCSTYPE=5
533  mc->CONFIG1.U = 0x5000; //AG_MOD=5
534  /* Set the range register */
535  mc->RANGE.U = (rangeSel << 15) | (rangeAddrUp << 7) | (rangeAddrLow << 0);
536  /* Run the tests */
537  mc->MCONTROL.U = 0xF201;
538  mc->MCONTROL.B.START = 0;
539  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
540  IfxScuWdt_setSafetyEndinit(password);
541 
542  /* wait for the end of the fill operation */
543  IfxMtu_waitForMbistDone(IfxMtu_sramTable[mbistSel].mbistDelay, 4, mbistSel);
544  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, mc->MSTATUS.B.DONE != 0);
545 
546  while (!IfxMtu_isMbistDone(mbistSel))
547  {
548  __nop();
549  }
550 
551  /* Clear EndInit Again */
552  IfxScuWdt_clearSafetyEndinit(password);
553 
554  /* Check the Fail Status */
555  if (mc->MSTATUS.B.FAIL)
556  {
557  /* Test has failed, check if any un-correctable error */
558  if (mc->ECCD.B.UERR)
559  {
560  /* Read the Error tracking register and return saying test failed */
561  *errorAddr = mc->ETRR[0].U;
562  retVal = 1U;
563  }
564  }
565 
566  /* Disable Memory Controller */
567  IfxMtu_disableMbistShell(mbistSel);
568 
569  /* for auto-init memories: wait for the end of the clear operation */
570  while (IfxMtu_isAutoInitRunning(mbistSel))
571  {}
572 
573  /* Restore the endinit state */
574  if (isEndInitEnabled == 1)
575  {
576  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
577  IfxScuWdt_setSafetyEndinit(password);
578  }
579 
580  return retVal;
581 }
582 
583 
584 static void IfxMtu_waitForMbistDone(uint32 towerDepth, uint8 numInstructions, IfxMtu_MbistSel mbistSel)
585 {
586  uint32 waitFact = (SCU_CCUCON0.B.SPBDIV / SCU_CCUCON0.B.SRIDIV) * numInstructions;
587  volatile uint32 waitTime;
588 
589  switch (mbistSel)
590  {
591  case IfxMtu_MbistSel_mcan:
592 
593  break;
594 
595  default:
596  break;
597  }
598 
599  if (numInstructions == 4)
600  {
601  waitTime = (towerDepth * waitFact) + 30;
602  }
603  else
604  {
605  waitTime = ((towerDepth / 4) * waitFact) + 30;
606  }
607 
608  waitTime = waitTime / 3;
609 
610  while (waitTime--)
611  {
612  __nop();
613  }
614 }
615 
616 
617 void IfxMtu_writeSramAddress(IfxMtu_MbistSel mbistSel, uint16 sramAddress)
618 {
619  Ifx_MC *mc = (Ifx_MC *)(IFXMTU_MC_ADDRESS_BASE + 0x100 * mbistSel);
620  uint8 isEndInitEnabled = 0;
621  uint16 password = 0;
622  password = IfxScuWdt_getSafetyWatchdogPassword();
623 
624  /* Check if the Endinit is cleared by application. If not, then handle it internally inside teh function.*/
625  if (IfxScuWdt_getSafetyWatchdogEndInit() == 1U)
626  {
627  /* Clear EndInit */
628  IfxScuWdt_clearSafetyEndinit(password);
629  isEndInitEnabled = 1;
630  }
631 
632  /* configure MBIST for single write opeation */
633  uint16 mcontrolMask = 0x4000; /* set USERED flag */
634  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DIR_OFF);
635  mc->CONFIG0.U = (1 << IFX_MC_CONFIG0_NUMACCS_OFF) | (0 << IFX_MC_CONFIG0_ACCSTYPE_OFF); /* 1 write access */
636  mc->CONFIG1.U = 0; /* ensure that linear scrambling is used */
637 
638  /* Set the address to be written (RAEN = 0) */
639  mc->RANGE.U = sramAddress;
640 
641  /* Start operation */
642  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DIR_OFF) | (1 << IFX_MC_MCONTROL_START_OFF);
643  mc->MCONTROL.U = mcontrolMask | (1 << IFX_MC_MCONTROL_DIR_OFF);
644 
645  if (isEndInitEnabled == 1)
646  {
647  /* Set EndInit Watchdog (to prevent Watchdog TO)*/
648  IfxScuWdt_setSafetyEndinit(password);
649  }
650 
651  /* Wait for the end of the operation */
652  IfxMtu_waitForMbistDone(IfxMtu_sramTable[mbistSel].mbistDelay, 1, mbistSel);
653  IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, mc->MSTATUS.B.DONE != 0);
654 
655  while (!IfxMtu_isMbistDone(mbistSel))
656  {
657  __nop();
658  }
659 }